Buswidth is now variable, based on widest register

Fixes #2.
2025-08-23 08:43:05 +00:00 · 2021-09-26 21:16:49 -07:00
parent 6359883c27
commit d3bfdeb3f0
10 changed files with 53 additions and 22 deletions
--- a/tests/systemrdl/simple_rw_reg.rdl
+++ b/tests/systemrdl/simple_rw_reg.rdl
@@ -1,5 +1,6 @@
 addrmap simple_rw_reg {
    reg {
+        regwidth = 64;
        field {sw=rw; hw=rw;} f1 [15:0];
        field {sw=rw; hw=rw;} f2 [31:16];
    } register_0 [2];