Add support for inline-comments

It is possible to enable them for:

- fields
- registers
- regfiles
- addrmaps

srdl2sv/cli/cli.py

@@ -85,6 +85,13 @@ class CliArguments():
             help="Define how many tabs or spaces will be contained\
                   in one level of indentation. (default: %(default)s)")
 
+        self.parser.add_argument(
+            "-i",
+            "--include_desc",
+            type=int,
+            default=0,
+            help="Include descriptions of addrmaps (+8), regfiles (+4), registers \
+                  (+2), and fields (+1) in RTL. This is a bitfield.")
 
         self.parser.add_argument(
             "IN_RDL",
@@ -97,12 +104,12 @@ class CliArguments():
 
         # Create dictionary to save config in
         config = dict()
-        config['list_args'] = list()
+        config['list_args'] = []
 
         # Save input file and output directory to dump everything in
         config['input_file'] = args.IN_RDL
         config['output_dir'] = args.out_dir
-        config['list_args'].append('Ouput Directory  : {}'.format(config['output_dir']))
+        config['list_args'].append(f"Ouput Directory  : {config['output_dir']}")
 
         # Create output directory
         try:
@@ -113,8 +120,8 @@ class CliArguments():
         # Map logging level string to integers
         config['stream_log_level'] = logging_map[args.stream_log_level]
         config['file_log_level'] = logging_map[args.file_log_level]
-        config['list_args'].append('Stream Log Level : {}'.format(args.stream_log_level))
+        config['list_args'].append(f"Stream Log Level : {args.stream_log_level}")
-        config['list_args'].append('File Log Level   : {}'.format(args.file_log_level))
+        config['list_args'].append(f"File Log Level   : {args.file_log_level}")
 
         # Determine paths to be passed to systemrdl-compiler to search
         # for include files.
@@ -131,26 +138,35 @@ class CliArguments():
 
         # Determine name of file to hold logs
         ts = time.strftime('%Y%m%d_%H%M%S', config['ts'])
-        config['file_log_location'] = "/".join([config['output_dir'], "srdl2sv_{}.log".format(ts)])
+        config['file_log_location'] = "/".join([config['output_dir'], f"srdl2sv_{ts}.log"])
 
         # Tab style
         config['real_tabs'] = args.real_tabs
         config['tab_width'] = args.tab_width
 
-        config['list_args'].append('Use Real Tabs    : {}'.format(config['real_tabs']))
+        config['list_args'].append(f"Use Real Tabs    : {config['real_tabs']}")
-        config['list_args'].append('Tab Width        : {}'.format(config['tab_width']))
+        config['list_args'].append(f"Tab Width        : {config['tab_width']}")
 
         # Set enums
         config['enums'] = not args.disable_enums
-        config['list_args'].append('Enums Enabled    : {}'.format(config['enums']))
+        config['list_args'].append(f"Enums Enabled    : {config['enums']}")
 
         # Set bus
         config['bus'] = args.bus
-        config['list_args'].append('Register Bus Type: {}'.format(config['bus']))
+        config['list_args'].append(f"Register Bus Type: {config['bus']}")
 
         if args.bus == 'amba3ahblite':
             config['addrwidth'] = 32
 
+        # Set location where descirptions shall be set
+        # Comparison to 1 to get a Python bool
+        config['descriptions'] = {}
+        config['descriptions']['addrmap'] = (args.include_desc >> 3) & 1 == 1
+        config['descriptions']['regfile'] = (args.include_desc >> 2) & 1 == 1
+        config['descriptions']['field'] = (args.include_desc >> 1) & 1 == 1
+        config['descriptions']['register'] = (args.include_desc >> 0) & 1 == 1
+        config['list_args'].append(f"Descriptions     : {config['descriptions']}")
+
         # Set version
         config['version'] = '0.01'
 

srdl2sv/components/addrmap.py

@@ -196,6 +196,9 @@ class AddrMap(Component):
                 inputs = '\n'.join(input_ports_rtl),
                 outputs = '\n'.join(output_ports_rtl)))
 
+        # Add description, if applicable
+        self.rtl_header.append(self.get_description())
+
         # Add wire/register instantiations
         self.__add_signal_instantiation()
 
@@ -390,3 +393,13 @@ class AddrMap(Component):
 
     def get_regwidth(self) -> int:
         return self.regwidth
+
+    def get_description(self):
+        if self.config['descriptions']['addrmap']:
+            if desc := self.obj.get_property('desc'):
+                return self.process_yaml(
+                        AddrMap.templ_dict['addrmap_desc'],
+                        {'desc': desc},
+                )
+
+        return ''

srdl2sv/components/component.py

@@ -318,3 +318,4 @@ class Component():
         path_underscored = path.replace('.', '__')
 
         return (owning_addrmap, full_path, path, path_underscored)
+

srdl2sv/components/field.py

@@ -41,6 +41,9 @@ class Field(Component):
         # Print a summary
         self.rtl_header.append(self.summary())
 
+        # Add description
+        self.rtl_header.append(self.get_description())
+
         # HW Access can be handled in __init__ function but SW access
         # must be handled in a seperate method that can be called
         # seperately in case of alias registers
@@ -1369,3 +1372,13 @@ class Field(Component):
             self.logger.error("It's not possible to combine the sticky(bit) "\
                               "property with the counter property. The counter property "\
                               "will be ignored.")
+
+    def get_description(self):
+        if self.config['descriptions']['field']:
+            if desc := self.obj.get_property('desc'):
+                return self.process_yaml(
+                        Field.templ_dict['field_desc'],
+                        {'desc': desc},
+                )
+
+        return ''

srdl2sv/components/regfile.py

@@ -103,6 +103,12 @@ class RegFile(Component):
             self.rtl_header.append("")
             self.rtl_header.append("generate")
 
+        # Add description, if applicable
+        self.rtl_header = [
+                self.get_description(),
+                *self.rtl_header
+            ]
+
         # Create comment and provide user information about register he/she
         # is looking at.
         self.rtl_header = [
@@ -261,3 +267,12 @@ class RegFile(Component):
     def get_regwidth(self) -> int:
         return self.regwidth
 
+    def get_description(self):
+        if self.config['descriptions']['regfile']:
+            if desc := self.obj.get_property('desc'):
+                return self.process_yaml(
+                        RegFile.templ_dict['regfile_desc'],
+                        {'desc': desc},
+                )
+
+        return ''

srdl2sv/components/register.py

@@ -93,6 +93,12 @@ class Register(Component):
             # regfile which create a generate
             self.__add_signal_instantiations()
 
+        # Add description, if applicable
+        self.rtl_header = [
+                self.get_description(),
+                *self.rtl_header
+            ]
+
         # Create comment and provide user information about register he/she is looking at
         self.rtl_header = [
             Register.templ_dict['reg_comment'].format(
@@ -567,3 +573,12 @@ class Register(Component):
     def get_regwidth(self) -> int:
         return self.obj.get_property('regwidth')
 
+    def get_description(self):
+        if self.config['descriptions']['register']:
+            if desc := self.obj.get_property('desc'):
+                return self.process_yaml(
+                        Register.templ_dict['reg_desc'],
+                        {'desc': desc},
+                )
+
+        return ''

srdl2sv/components/templates/addrmap.yaml

@@ -58,6 +58,14 @@ header: |-
    * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
    * OTHER DEALINGS IN THE SOFTWARE.
    ****************************************************************/
+addrmap_desc: 
+    rtl: |-
+
+      /*******************************************************************
+      /**ADDRMAP DESCRIPTION**********************************************
+      /*******************************************************************
+      {desc}
+      /*******************************************************************/
 
 module_declaration: 
     rtl: |-

srdl2sv/components/templates/fields.yaml

@@ -171,6 +171,12 @@ field_comment:
         // flags      : {misc_flags}
         // external   : {external}
         //-----------------------------------------------
+field_desc: 
+    rtl: |-
+
+        /********************DESCRIPTION*****************
+        {desc}
+        /************************************************/
 combo_operation_comment: 
     rtl: |-
 

srdl2sv/components/templates/regfile.yaml

@@ -8,6 +8,12 @@ regfile_comment:
          * DEPTHS (per dimension): {depth}
          *******************************************************************
          *******************************************************************/
+regfile_desc: 
+    rtl: |-
+
+      /**REGISTER DESCRIPTION*********************************************
+      {desc}
+      /*******************************************************************/
 generate_for_start: 
     rtl: |-
         for ({iterator} = 0; {iterator} < {limit}; {iterator}++)

srdl2sv/components/templates/register.yaml

@@ -53,12 +53,18 @@ rw_wire_assign_any_alias:
 reg_comment: |-
 
     /*******************************************************************
-     *******************************************************************
+    /*******************************************************************
-     * REGISTER              : {name}
+    /* REGISTER              : {name}
-     * DIMENSION             : {dimensions}
+    /* DIMENSION             : {dimensions}
-     * DEPTHS (per dimension): {depth}
+    /* DEPTHS (per dimension): {depth}
-     *******************************************************************
+    /*******************************************************************
-     *******************************************************************/
+    /*******************************************************************/
+reg_desc: 
+    rtl: |-
+
+      /**REGISTER DESCRIPTION*********************************************
+      {desc}
+      /*******************************************************************/
 generate_for_start: |-
     for ({iterator} = 0; {iterator} < {limit}; {iterator}++)
     begin