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Update AMBA 3 AHB Lite widget in examples with 33c92c8 (issue #9)

This commit is contained in:
Dennis Potter 2021-10-30 23:35:38 -07:00
parent 33c92c8994
commit ed167c05de
Signed by: Dennis
GPG Key ID: 186A8AD440942BAF
6 changed files with 33 additions and 24 deletions
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4
examples/hierarchical_regfiles/srdl2sv_out/hierarchical_regfiles.sv
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@ -14,13 +14,13 @@
* srdl2sv itself is licensed under GPLv3.
*
* Maintainer : Dennis Potter <dennis@dennispotter.eu>
* Report Bugs: https://git.dennispotter.eu/Dennis/srdl2sv/issues
* Report Bugs: https://github.com/Silicon1602/srdl2sv/issues
*
* ===GENERATION INFORMATION======================================
*
* Generation information:
* - User: : dpotter
* - Time : October 30 2021 19:38:01
* - Time : October 30 2021 23:34:40
* - Path : /home/dpotter/srdl2sv/examples/hierarchical_regfiles
* - RDL file : ['hierarchical_regfiles.rdl']
* - Hostname : ArchXPS

15
examples/hierarchical_regfiles/srdl2sv_out/srdl2sv_amba3ahblite.sv
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@ -135,7 +135,7 @@ module srdl2sv_amba3ahblite #(
begin
// Defaults
HREADYOUT = 1'b1;
HRESP = 1'b0;
HRESP = OKAY;
// When reading back, the data of the bit that was accessed over the bus
// should be at byte 0 of the HRDATA bus and bits that were not accessed
@ -174,15 +174,17 @@ module srdl2sv_amba3ahblite #(
widget_if_w_vld_next = operation_q == WRITE;
widget_if_r_vld_next = operation_q == READ;
if (widget_if.err && widget_if.rdy)
begin
fsm_next = FSM_ERR_0;
end
else if (HTRANS == BUSY)
if (HTRANS == BUSY)
begin
// Wait
fsm_next = FSM_TRANS;
end
else if (widget_if.err && widget_if.rdy)
begin
HREADYOUT = 0;
HRESP = ERROR;
fsm_next = FSM_ERR_1;
end
else if (HTRANS == NONSEQ)
begin
// Another unrelated access is coming
@ -307,3 +309,4 @@ module srdl2sv_amba3ahblite #(
endmodule

4
examples/interrupt_hierarchy/srdl2sv_out/interrupt_hierarchy.sv
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@ -14,13 +14,13 @@
* srdl2sv itself is licensed under GPLv3.
*
* Maintainer : Dennis Potter <dennis@dennispotter.eu>
* Report Bugs: https://git.dennispotter.eu/Dennis/srdl2sv/issues
* Report Bugs: https://github.com/Silicon1602/srdl2sv/issues
*
* ===GENERATION INFORMATION======================================
*
* Generation information:
* - User: : dpotter
* - Time : October 30 2021 19:37:23
* - Time : October 30 2021 23:34:49
* - Path : /home/dpotter/srdl2sv/examples/interrupt_hierarchy
* - RDL file : ['interrupt_hierarchy.rdl']
* - Hostname : ArchXPS

15
examples/interrupt_hierarchy/srdl2sv_out/srdl2sv_amba3ahblite.sv
View File

@ -135,7 +135,7 @@ module srdl2sv_amba3ahblite #(
begin
// Defaults
HREADYOUT = 1'b1;
HRESP = 1'b0;
HRESP = OKAY;
// When reading back, the data of the bit that was accessed over the bus
// should be at byte 0 of the HRDATA bus and bits that were not accessed
@ -174,15 +174,17 @@ module srdl2sv_amba3ahblite #(
widget_if_w_vld_next = operation_q == WRITE;
widget_if_r_vld_next = operation_q == READ;
if (widget_if.err && widget_if.rdy)
begin
fsm_next = FSM_ERR_0;
end
else if (HTRANS == BUSY)
if (HTRANS == BUSY)
begin
// Wait
fsm_next = FSM_TRANS;
end
else if (widget_if.err && widget_if.rdy)
begin
HREADYOUT = 0;
HRESP = ERROR;
fsm_next = FSM_ERR_1;
end
else if (HTRANS == NONSEQ)
begin
// Another unrelated access is coming
@ -307,3 +309,4 @@ module srdl2sv_amba3ahblite #(
endmodule

4
examples/simple_rw_reg/srdl2sv_out/simple_rw_reg.sv
View File

@ -14,13 +14,13 @@
* srdl2sv itself is licensed under GPLv3.
*
* Maintainer : Dennis Potter <dennis@dennispotter.eu>
* Report Bugs: https://git.dennispotter.eu/Dennis/srdl2sv/issues
* Report Bugs: https://github.com/Silicon1602/srdl2sv/issues
*
* ===GENERATION INFORMATION======================================
*
* Generation information:
* - User: : dpotter
* - Time : October 30 2021 19:37:29
* - Time : October 30 2021 23:34:53
* - Path : /home/dpotter/srdl2sv/examples/simple_rw_reg
* - RDL file : ['simple_rw_reg.rdl']
* - Hostname : ArchXPS

15
examples/simple_rw_reg/srdl2sv_out/srdl2sv_amba3ahblite.sv
View File

@ -135,7 +135,7 @@ module srdl2sv_amba3ahblite #(
begin
// Defaults
HREADYOUT = 1'b1;
HRESP = 1'b0;
HRESP = OKAY;
// When reading back, the data of the bit that was accessed over the bus
// should be at byte 0 of the HRDATA bus and bits that were not accessed
@ -174,15 +174,17 @@ module srdl2sv_amba3ahblite #(
widget_if_w_vld_next = operation_q == WRITE;
widget_if_r_vld_next = operation_q == READ;
if (widget_if.err && widget_if.rdy)
begin
fsm_next = FSM_ERR_0;
end
else if (HTRANS == BUSY)
if (HTRANS == BUSY)
begin
// Wait
fsm_next = FSM_TRANS;
end
else if (widget_if.err && widget_if.rdy)
begin
HREADYOUT = 0;
HRESP = ERROR;
fsm_next = FSM_ERR_1;
end
else if (HTRANS == NONSEQ)
begin
// Another unrelated access is coming
@ -307,3 +309,4 @@ module srdl2sv_amba3ahblite #(
endmodule