Change way the order of RTL is determined
By using a dictionary, it will be easier to mix & match the RTL order dependend on the properties of the field. This commit also adds anded/ored/xored properties.
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parent
861a020aff
commit
f1d9ba2656
GPG Key ID:
186A8AD440942BAF
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@ -1,10 +1,10 @@
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import yaml
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import math
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import yaml
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from systemrdl import RDLCompiler, RDLCompileError, RDLWalker, RDLListener, node
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from systemrdl.node import FieldNode
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from systemrdl.rdltypes import PrecedenceType, AccessType
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from itertools import chain
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TAB = " "
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@ -18,6 +18,10 @@ class Field:
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self.rtl = []
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self.bytes = math.ceil(obj.width / 8)
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# Make a list of I/O that shall be added to the addrmap
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self.input_ports = []
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self.output_ports = []
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##################################################################################
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# LIMITATION:
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# v1.x of the systemrdl-compiler does not support non-homogeneous arrays.
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@ -43,7 +47,6 @@ class Field:
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rst_negl = ""
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rst_active = "active_high"
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print(obj.get_property('reset'))
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# Value of reset?
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rst_value = '\'x' if obj.get_property("reset") == None else obj.get_property('reset')
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except:
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@ -104,12 +107,23 @@ class Field:
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indent_lvl += 1
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# Define hardware access (if applicable)
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hw_access_rtl = []
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# Not all access types are required and the order might differ
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# depending on what types are defined and what precedence is
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# set. Therefore, first add all RTL into a dictionary and
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# later place it in the right order.
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#
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# The following RTL blocks are defined:
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# - hw_write --> write access for the hardware interface
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# - sw_write --> write access for the software interface
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#
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access_rtl = dict([])
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if hw_access == AccessType.rw or hw_access == AccessType.w:
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# Define hardware access (if applicable)
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access_rtl['hw_write'] = []
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if hw_access in (AccessType.rw, AccessType.w):
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if obj.get_property('we') or obj.get_property('wel'):
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hw_access_rtl.append(
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access_rtl['hw_write'].append(
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Field.templ_dict['hw_access_we_wel'].format(
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negl = '!' if obj.get_property('wel') else '',
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reg_name = obj.parent.inst_name,
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@ -117,7 +131,7 @@ class Field:
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genvars = genvars_str,
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indent = self.indent(indent_lvl)))
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hw_access_rtl.append(
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access_rtl['hw_write'].append(
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Field.templ_dict['hw_access_field'].format(
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reg_name = obj.parent.inst_name,
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field_name = obj.inst_name,
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@ -125,45 +139,52 @@ class Field:
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indent = self.indent(indent_lvl)))
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# Define software access (if applicable)
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sw_access_rtl = []
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access_rtl['sw_write'] = []
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# TODO: if sw_access_enabled
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sw_access_rtl.append(
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Field.templ_dict['sw_access_field'].format(
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reg_name = obj.parent.inst_name,
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field_name = obj.inst_name,
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genvars = genvars_str,
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indent = self.indent(indent_lvl)))
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indent_lvl += 1
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# If field spans multiple bytes, every byte shall have a seperate enable!
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for i in range(self.bytes):
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sw_access_rtl.append(
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Field.templ_dict['sw_access_byte'].format(
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if sw_access in (AccessType.rw, AccessType.w):
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access_rtl['sw_write'].append(
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Field.templ_dict['sw_access_field'].format(
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reg_name = obj.parent.inst_name,
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field_name = obj.inst_name,
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genvars = genvars_str,
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i = i,
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indent = self.indent(indent_lvl)))
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sw_access_rtl.append("")
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indent_lvl += 1
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indent_lvl -= 1
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# If field spans multiple bytes, every byte shall have a seperate enable!
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for i in range(self.bytes):
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access_rtl['sw_write'].append(
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Field.templ_dict['sw_access_byte'].format(
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reg_name = obj.parent.inst_name,
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field_name = obj.inst_name,
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genvars = genvars_str,
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i = i,
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indent = self.indent(indent_lvl)))
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sw_access_rtl.append("{}end".format(self.indent(indent_lvl)))
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indent_lvl -= 1
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access_rtl['sw_write'].append("{}end".format(self.indent(indent_lvl)))
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# Define else with correct indentation and add to dictionary
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access_rtl['else'] = ["{}else".format(self.indent(indent_lvl))]
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# Add empty string
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access_rtl[''] = ['']
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# Check if hardware has precedence (default `precedence = sw`)
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if precedence == 'PrecedenceType.sw':
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self.rtl = [*self.rtl,
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*sw_access_rtl,
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'{}else'.format(self.indent(indent_lvl)),
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*hw_access_rtl]
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rtl_order = ['sw_write',
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'else' if len(access_rtl['hw_write']) > 0 else '',
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'hw_write']
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else:
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self.rtl = [*self.rtl,
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*sw_access_rtl,
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'{}else'.format(self.indent(indent_lvl)),
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*hw_access_rtl]
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rtl_order = ['hw_write',
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'else' if len(access_rtl['sw_write']) > 0 else '',
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'sw_write']
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# Add dictionary to main RTL list in correct order
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self.rtl = [
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*self.rtl,
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*chain.from_iterable([access_rtl[i] for i in rtl_order])]
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indent_lvl -= 1
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@ -173,6 +194,36 @@ class Field:
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field_name = obj.inst_name,
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indent = self.indent(indent_lvl)))
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#####################
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# Add combo logic
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#####################
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operations = []
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if obj.get_property('anded'):
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operations.append(['anded', '&'])
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if obj.get_property('ored'):
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operations.append(['ored', '|'])
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if obj.get_property('xored'):
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operations.append(['xored', '^'])
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if len(operations) > 0:
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self.rtl.append(
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Field.templ_dict['combo_operation_comment'].format(
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reg_name = obj.parent.inst_name,
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field_name = obj.inst_name,
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indent = self.indent(indent_lvl)))
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self.rtl = [
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*self.rtl,
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*[Field.templ_dict['assign_combo_operation'].format(
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field_name = obj.inst_name,
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reg_name = obj.parent.inst_name,
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genvars = genvars_str,
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op_name = i[0],
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op_verilog = i[1],
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indent = self.indent(indent_lvl)) for i in operations]]
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# TODO: Set sanity checks. For example, having no we but precedence = hw
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# will cause weird behavior.
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@staticmethod
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@ -13,6 +13,7 @@ sw_access_field: |-
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sw_access_byte: |-
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{indent}if (byte_enable[{i}])
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{indent} {reg_name}_{field_name}_q{genvars}[8*({i}+1)-1 -: 8] <= sw_wr_bus[8*({i}+1)-1 -: 8];
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hw_access_we_wel: |-
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{indent}if ({negl}{reg_name}_{field_name}_hw_wr{genvars})
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hw_access_field: |-
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@ -29,3 +30,9 @@ field_comment: |-
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{indent}// sw = {sw_access} {sw_precedence}
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{indent}// reset : {rst_active} / {rst_type}
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{indent}//-----------------------------------------------
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combo_operation_comment: |-
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{indent}// Combinational logic for {reg_name}_{field_name}
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assign_combo_operation: |-
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{indent}assign {reg_name}_{field_name}_{op_name}{genvars} = {op_verilog}{reg_name}_{field_name}_q{genvars}
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