Dennis/srdl2sv
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A SystemRDL 2.0 to (synthesizable) SystemVerilog compiler.
2 Commits 1 Branch 0 Tags 713 KiB
Python 92.9%
SystemVerilog 5.7%
Makefile 1.4%
f1d9ba2656
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Dennis f1d9ba2656
Change way the order of RTL is determined 
By using a dictionary, it will be easier to mix & match the RTL
order dependend on the properties of the field.

This commit also adds anded/ored/xored properties.
2021-05-04 00:23:14 +02:00
srdl2sv Change way the order of RTL is determined 2021-05-04 00:23:14 +02:00
.gitignore Initial commit of SRDL2SV 2021-05-02 00:58:43 +02:00
LIMITATIONS.md Initial commit of SRDL2SV 2021-05-02 00:58:43 +02:00