mirror of
https://github.com/Silicon1602/srdl2sv.git
synced 2024-12-22 06:58:41 +00:00
Add check for uniqueness of enum member names within a scope
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parent
ec492d619a
commit
f4432f5b49
@ -1,5 +1,6 @@
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import re
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import importlib.resources as pkg_resources
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from sys import exit
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import yaml
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from systemrdl import node
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@ -127,14 +128,21 @@ class AddrMap(Component):
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output_ports_rtl[-1] = output_ports_rtl[-1].rstrip(',')
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import_package_list = []
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[import_package_list.append(
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AddrMap.templ_dict['import_package']['rtl'].format(
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name = self.name)) for x in self.get_package_names()]
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try:
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import_package_list = [[
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AddrMap.templ_dict['import_package']['rtl'].format(
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name = self.name),
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',\n'
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] for x in self.get_package_names()][0][:-1]
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import_package_list.append(';')
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except IndexError:
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pass
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self.rtl_header.append(
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AddrMap.templ_dict['module_declaration']['rtl'].format(
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name = self.name,
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import_package_list = ',\n'.join(import_package_list),
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import_package_list = ''.join(import_package_list),
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resets = '\n'.join(reset_ports_rtl),
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inputs = '\n'.join(input_ports_rtl),
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outputs = '\n'.join(output_ports_rtl)))
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@ -191,11 +199,18 @@ class AddrMap(Component):
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return names
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def get_package_rtl(self, tab_width: int = 4, real_tabs = False) -> dict():
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if not self.config['enums']:
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return dict()
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# First go through all registers in this scope to generate a package
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package_rtl = []
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enum_rtl = []
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rtl_return = dict()
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# Need to keep track of enum names since they shall be unique
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# per scope
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enum_members = dict()
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for i in self.registers.values():
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for key, value in i.get_typedefs().items():
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variable_list = []
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@ -204,6 +219,25 @@ class AddrMap(Component):
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max([len(x[0]) for x in value.members]), 40)
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for var in value.members:
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if var[0] not in enum_members:
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enum_members[var[0]] = "::".join([self.name, key])
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else:
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self.logger.fatal(
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"Enum member '{}' was found at multiple locations in the same "\
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"main scope: \n"\
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" -- 1st occurance: '{}'\n"\
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" -- 2nd occurance: '{}'\n\n"\
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"This is not legal because all these enums will be defined "\
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"in the same SystemVerilog scope. To share the same enum among "\
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"different registers, define them on a higher level in the "\
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"hierarchy.\n\n"\
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"Exiting...".format(
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var[0],
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enum_members[var[0]],
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"::".join([self.name, key])))
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exit(1)
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variable_list.append(
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AddrMap.templ_dict['enum_var_list_item']['rtl'].format(
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value = var[1],
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@ -2,7 +2,7 @@
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module_declaration:
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rtl: |-
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module {name}
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{import_package_list};
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{import_package_list}
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(
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// Clock & Resets
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input reg_clk,
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