mirror of
https://github.com/Silicon1602/srdl2sv.git
synced 2025-04-19 13:02:57 +00:00
Dennis
085e2ea2dc
Now, every snippet of RTL in the YAML file can also hold internal variables (i.e., signals), input or output ports. Furthermore, the input/output port lists are replaced by a dictionary to prevent duplicate entries.
51 lines
1.7 KiB
YAML
51 lines
1.7 KiB
YAML
---
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rw_wire_assign_1_dim:
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rtl: |
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// Assign register-activation signals
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assign {path}_reg_active{genvars} = addr == {addr};
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assign {path}_sw_wr = {path}_reg_active && r_vld;
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assign {path}_sw_rd = {path}_reg_active && w_vld;
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signals:
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- name: '{path}_sw_wr'
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signal_type: 'logic'
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- name: '{path}_sw_rd'
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signal_type: 'logic'
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- name: '{path}_reg_active'
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signal_type: 'logic'
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input_ports:
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output_ports:
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rw_wire_assign_multi_dim:
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rtl: |
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// Assign register-activation signals
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assign {path}_reg_active{genvars} = addr == ({addr}+({genvars_sum})*{stride});
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assign {path}_sw_wr{genvars} = {path}_reg_active{genvars} && r_vld;
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assign {path}_sw_rd{genvars} = {path}_reg_active{genvars} && w_vld;
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signals:
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- name: '{path}_sw_wr'
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signal_type: 'logic'
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- name: '{path}_sw_rd'
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signal_type: 'logic'
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- name: '{path}_reg_active'
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signal_type: 'logic'
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input_ports:
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output_ports:
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reg_comment: |-
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/*******************************************************************
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*******************************************************************
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* REGISTER : {name}
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* DIMENSION : {dimensions}
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* DEPTHS (per dimension): {depth}
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*******************************************************************
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*******************************************************************/
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generate_for_start: |-
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for ({iterator} = 0; {iterator} < {limit}; {iterator}++)
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begin
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generate_for_end: |-
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end // of for loop with iterator {dimension}
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signal_declaration: |-
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{type:10s}{name:20s} {unpacked_dim};
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