Dennis 085e2ea2dc

Provide more advanced way of adding internal signals or ports ...

Now, every snippet of RTL in the YAML file can also hold internal
variables (i.e., signals), input or output ports. Furthermore, the
input/output port lists are replaced by a dictionary to prevent
duplicate entries.

2021-05-23 17:46:48 +02:00

srdl2sv

Provide more advanced way of adding internal signals or ports

2021-05-23 17:46:48 +02:00

.gitignore

Initial commit of SRDL2SV

2021-05-02 00:58:43 +02:00

LIMITATIONS.md

Initial commit of SRDL2SV

2021-05-02 00:58:43 +02:00

Description

A SystemRDL 2.0 to (synthesizable) SystemVerilog compiler.

asicfpgahardware-description-languagehdlrdlregister-description-languageregisterssystemrdlsystemrdl-compilersystemverilogverilog

713 KiB

Languages

Python 92.9%

SystemVerilog 5.7%

Makefile 1.4%