mirror of
https://github.com/Silicon1602/srdl2sv.git
synced 2025-04-19 13:02:57 +00:00
359 lines
11 KiB
Python
359 lines
11 KiB
Python
import re
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import sys
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from itertools import chain
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from typing import NamedTuple
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from systemrdl import node
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from dataclasses import dataclass
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# Local modules
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from log.log import create_logger
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# Define NamedTuple
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class TypeDef(NamedTuple):
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scope: str
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width: int
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members: tuple
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@dataclass
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class SWMuxEntry:
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data_wire: str
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rdy_wire: str
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err_wire: str
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active_wire: str
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@dataclass
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class SWMuxEntryDimensioned():
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mux_entry: SWMuxEntry
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dim: str
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class Component():
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def __init__(self, obj, config):
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self.rtl_header = []
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self.rtl_footer = []
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self.children = dict()
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self.typedefs = dict()
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self.ports = dict()
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self.resets = set()
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self.signals = dict()
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self.ports['input'] = dict()
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self.ports['output'] = dict()
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self.field_type = ''
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# Save object
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# TODO: should probably be list because of alias registers
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self.obj = obj
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# Save name
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self.name = obj.inst_name
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# Create path
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self.create_underscored_path()
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# Save config
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self.config = config.copy()
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# By default, registers and fields are not interrupt registers
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self.properties = {
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'intr': False,
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'halt': False,
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'swmod': False,
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'swacc': False,
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'sw_rd': False,
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'sw_wr': False,
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'sw_rd_wire': False,
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'sw_wr_wire': False,
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}
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# Create logger object
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self.create_logger("{}".format(self.full_path), config)
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self.logger.debug('Starting to process {} "{}"'.format(
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self.__class__.__name__,
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obj.inst_name))
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def create_logger(self, name: str, config: dict):
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self.logger = create_logger(
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"{}".format(name),
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stream_log_level=config['stream_log_level'],
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file_log_level=config['file_log_level'],
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file_name=config['file_log_location'])
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self.logger.propagate = False
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def get_resets(self):
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self.logger.debug("Return reset list")
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for x in self.children.values():
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self.resets |= x.get_resets()
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return self.resets
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def get_ports(self, port_type: str):
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self.logger.debug("Return port list")
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for x in self.children.values():
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self.ports[port_type] |= x.get_ports(port_type)
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return self.ports[port_type]
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def get_max_dim_depth(self) -> int:
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self.logger.debug("Return depth '{}' for dimensions (including "\
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"parents) '{}'".format(self.total_dimensions,
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self.total_array_dimensions))
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return max([
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self.total_dimensions,
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*[x.get_max_dim_depth() for x in self.children.values()]
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])
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def get_signals(self, no_children = False):
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self.logger.debug("Return signal list")
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if not no_children:
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for x in self.children.values():
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self.signals |= x.get_signals()
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return self.signals
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def get_typedefs(self):
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self.logger.debug("Return typedef list")
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for x in self.children.values():
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self.typedefs |= x.get_typedefs()
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return self.typedefs
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def get_rtl(self, tab_width: int = 0, real_tabs: bool = False) -> str:
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self.logger.debug("Return RTL")
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# Loop through children and append RTL
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rtl_children = []
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for x in self.children.values():
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rtl_children.append(x.get_rtl())
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# Concatenate header, main, and footer
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rtl = [*self.rtl_header, *rtl_children, *self.rtl_footer]
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# Join lists and return string
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if tab_width > 0:
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return Component.add_tabs(
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'\n'.join(rtl),
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tab_width,
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real_tabs)
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return '\n'.join(rtl)
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@staticmethod
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def add_tabs(rtl: str, tab_width: int = 4, real_tabs = False) -> str:
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indent_lvl = 0
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indent_lvl_next = 0
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# Define tab style
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tab = "\t" if real_tabs else " "
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tab = tab_width * tab
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# Define triggers for which the indentation level will increment or
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# decrement on the next line
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trigger_re = re.compile(r"""
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.*?(
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(?:\bbegin\b|\{|\bcase\b|<<INDENT>>)|
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(?:\bend\b|}|\bendcase\b|<<UNINDENT>>)
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)([^$]*)
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""", flags=re.VERBOSE)
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rtl_indented = []
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# Go through RTL, line by line
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for line in rtl.split('\n', -1):
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line_split = line
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# This is done because the increment of the indent level must
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# be delayed one cycle
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indent_lvl = indent_lvl_next
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while 1:
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# Check if indentation must be decremented
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matchObj = trigger_re.match(line_split)
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if matchObj:
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if matchObj.group(1) in ('begin', '{', 'case', '<<INDENT>>'):
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indent_lvl_next += 1
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else:
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indent_lvl = indent_lvl_next - 1
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indent_lvl_next -= 1
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line_split = matchObj.group(2)
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if not line_split:
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break
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else:
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break
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# Add tabs
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if line.strip() not in ("<<INDENT>>", "<<UNINDENT>>", "<<SQUASH_NEWLINE>>"):
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rtl_indented.append("{}{}".format(tab*indent_lvl, line))
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return '\n'.join(rtl_indented)
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@staticmethod
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def get_underscored_path(path: str, owning_addrmap: str):
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return path\
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.replace('[]', '')\
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.replace('{}.'.format(owning_addrmap), '')\
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.replace('.', '__')
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@staticmethod
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def split_dimensions(path: str):
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re_dimensions = re.compile('(\[[^]]*\])')
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new_path = re_dimensions.sub('', path)
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return (new_path, ''.join(re_dimensions.findall(path)))
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def get_signal_name(self, obj):
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name = []
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try:
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child_obj = obj.node
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except AttributeError:
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child_obj = obj
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split_name = Component.split_dimensions(
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Component.get_underscored_path(
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child_obj.get_path(),
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child_obj.owning_addrmap.inst_name)
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)
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name.append(split_name[0])
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if isinstance(obj, node.FieldNode):
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name.append('_q')
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elif isinstance(obj, node.SignalNode):
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# Must add it to signal list
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self.ports['input'][obj.inst_name] =\
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("logic" if obj.width == 1 else 'logic [{}:0]'.format(obj.width), [])
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else:
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name.append('_')
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name.append(obj.name)
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# This is a property. Check if the original field actually has this property
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if obj.name == "intr" or obj.name == "halt":
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pass
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elif not obj.node.get_property(obj.name):
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self.logger.fatal("Reference to the property '{}' of instance '{}' found. "
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"This instance does hold the reference property! Please "
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"fix this if you want me to do my job properly."
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.format(obj.name, obj.node.get_path()))
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sys.exit(1)
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name.append(split_name[1])
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return ''.join(name)
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def process_yaml(self,
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yaml_obj,
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values: dict = {},
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skip_signals: bool = False,
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skip_inputs: bool = False,
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skip_outputs: bool = False):
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try:
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if skip_signals:
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raise KeyError
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for x in yaml_obj['signals']:
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try:
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array_dimensions = [] if x['no_unpacked'] else self.total_array_dimensions
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except KeyError:
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array_dimensions = self.total_array_dimensions
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self.signals[x['name'].format(**values)] =\
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(x['signal_type'].format(**values),
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array_dimensions)
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except (TypeError, KeyError):
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pass
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try:
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if skip_inputs:
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raise KeyError
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for x in yaml_obj['input_ports']:
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try:
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array_dimensions = [] if x['no_unpacked'] else self.total_array_dimensions
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except KeyError:
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array_dimensions = self.total_array_dimensions
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self.ports['input'][x['name'].format(**values)] =\
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(x['signal_type'].format(**values),
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array_dimensions)
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except (TypeError, KeyError):
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pass
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try:
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if skip_outputs:
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raise KeyError
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for x in yaml_obj['output_ports']:
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try:
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array_dimensions = [] if x['no_unpacked'] else self.total_array_dimensions
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except KeyError:
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array_dimensions = self.total_array_dimensions
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self.ports['output'][x['name'].format(**values)] =\
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(x['signal_type'].format(**values),
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array_dimensions)
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except (TypeError, KeyError):
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pass
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# Return RTL with values
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return yaml_obj['rtl'].format(**values)
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@staticmethod
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def process_reset_signal(reset_signal):
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rst = dict()
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try:
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rst['name'] = reset_signal.inst_name
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rst['async'] = reset_signal.get_property("async")
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rst['type'] = "asynchronous" if rst['async'] else "synchronous"
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# Active low or active high?
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if reset_signal.get_property("activelow"):
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rst['edge'] = "negedge"
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rst['active'] = "active_low"
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else:
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rst['edge'] = "posedge"
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rst['active'] = "active_high"
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except:
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rst['async'] = False
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rst['name'] = None
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rst['edge'] = None
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rst['value'] = "'x"
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rst['active'] = "-"
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rst['type'] = "-"
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return rst
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def create_underscored_path(self):
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self.owning_addrmap, self.full_path, self.path, self.path_underscored =\
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Component.create_underscored_path_static(self.obj)
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@staticmethod
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def create_underscored_path_static(obj):
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owning_addrmap = obj.owning_addrmap.inst_name
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full_path = Component.split_dimensions(obj.get_path())[0]
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path = full_path\
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.replace('{}.'.format(owning_addrmap), '')
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path_underscored = path.replace('.', '__')
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return (owning_addrmap, full_path, path, path_underscored)
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def get_description(self):
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if self.config['descriptions'][self.__class__.__name__]:
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if desc := self.obj.get_property('desc'):
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return self.process_yaml(
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self.templ_dict['description'],
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{'desc': desc},
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)
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return ''
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