Dennis/srdl2sv
1
0
Fork 0
mirror of https://github.com/Silicon1602/srdl2sv.git synced 2024-12-22 06:58:41 +00:00
Code Issues Projects Releases Wiki Activity

Replace SW Mux Entry by a dataclass, rather than an (unnamed) tuple

Browse Source
This commit is contained in:
Dennis Potter 2021-10-19 23:58:02 -07:00
parent d80224c43d
commit 1b011ff593
Signed by: Dennis
GPG Key ID: 186A8AD440942BAF
5 changed files with 61 additions and 43 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
srdl2sv/components/addrmap.py
View File

@ -221,30 +221,20 @@ class AddrMap(Component):
self.rtl_footer.append('endmodule')
def __create_mux_string(self):
#TODO: For optimal synthesis results, think about using 1B offsets rather than awkard 4B.
# for byte-access, byte-enables are used anyway
list_of_cases = []
# Add an entry for each version of a register
for child in self.children.values():
for mux_entry in child.create_mux_string():
for mux_entry_dim in child.create_mux_string():
# Data structure of mux_entry:
# mux_entry[0] --> names of data/rdy/err wire and start addr
# [0] --> data_mux (str)
# [1] --> rdy_mux (str)
# [2] --> err_mux (str)
# [3] --> activate_wire (str)
# mux_entry[1] --> String of array index that represents offset (str)
r2b_data = ''.join([mux_entry[0][0], mux_entry[1]])
r2b_rdy = ''.join([mux_entry[0][1], mux_entry[1]])
r2b_err = ''.join([mux_entry[0][2], mux_entry[1]])
activate_wire = ''.join([mux_entry[0][3], mux_entry[1]])
r2b_data = ''.join([mux_entry_dim.mux_entry.data_wire, mux_entry_dim.dim])
r2b_rdy = ''.join([mux_entry_dim.mux_entry.rdy_wire, mux_entry_dim.dim])
r2b_err = ''.join([mux_entry_dim.mux_entry.err_wire, mux_entry_dim.dim])
active_wire = ''.join([mux_entry_dim.mux_entry.active_wire, mux_entry_dim.dim])
list_of_cases.append(
AddrMap.templ_dict['list_of_mux_cases']['rtl'].format(
activate_wire = activate_wire,
active_wire = active_wire,
r2b_data = r2b_data,
r2b_rdy = r2b_rdy,
r2b_err = r2b_err)

13
srdl2sv/components/component.py
View File

@ -3,6 +3,7 @@ import sys
from itertools import chain
from typing import NamedTuple
from systemrdl import node
from dataclasses import dataclass
# Local modules
from log.log import create_logger
@ -13,6 +14,18 @@ class TypeDef(NamedTuple):
width: int
members: tuple
@dataclass
class SWMuxEntry:
data_wire: str
rdy_wire: str
err_wire: str
active_wire: str
@dataclass
class SWMuxEntryDimensioned():
mux_entry: SWMuxEntry
dim: str
class Component():
def __init__(self, obj, config):
self.rtl_header = []

25
srdl2sv/components/memory.py
View File

@ -9,7 +9,7 @@ from systemrdl.node import FieldNode
from systemrdl.rdltypes import AccessType
# Local packages
from components.component import Component
from components.component import Component, SWMuxEntry, SWMuxEntryDimensioned
from . import templates
@ -136,21 +136,21 @@ class Memory(Component):
def __add_sw_mux_assignments(self):
# Create list of mux-inputs to later be picked up by carrying addrmap
self.sw_mux_assignment_var_name = \
(
self.process_yaml(
SWMuxEntry (
data_wire = self.process_yaml(
Memory.templ_dict['sw_data_assignment_var_name'],
{'path': self.path_underscored,
'accesswidth': self.memwidth - 1}
),
self.process_yaml(
rdy_wire = self.process_yaml(
Memory.templ_dict['sw_rdy_assignment_var_name'],
{'path': self.path_underscored}
),
self.process_yaml(
err_wire = self.process_yaml(
Memory.templ_dict['sw_err_assignment_var_name'],
{'path': self.path_underscored}
),
f"{self.path_underscored}_mem_active"
active_wire = f"{self.path_underscored}_mem_active"
)
if self.obj.get_property('sw') == AccessType.rw:
@ -164,16 +164,21 @@ class Memory(Component):
self.process_yaml(
self.templ_dict[access_type],
{'path': self.path_underscored,
'sw_data_assignment_var_name': self.sw_mux_assignment_var_name[0],
'sw_rdy_assignment_var_name': self.sw_mux_assignment_var_name[1],
'sw_err_assignment_var_name': self.sw_mux_assignment_var_name[2],
'sw_data_assignment_var_name': self.sw_mux_assignment_var_name.data_wire,
'sw_rdy_assignment_var_name': self.sw_mux_assignment_var_name.rdy_wire,
'sw_err_assignment_var_name': self.sw_mux_assignment_var_name.err_wire,
}
),
''
]
def create_mux_string(self):
yield(self.sw_mux_assignment_var_name, '')
yield(
SWMuxEntryDimensioned(
mux_entry = self.sw_mux_assignment_var_name,
dim = ''
)
)
def get_regwidth(self) -> int:
return self.memwidth

42
srdl2sv/components/register.py
View File

@ -7,7 +7,7 @@ import itertools
from systemrdl import node
# Local modules
from components.component import Component
from components.component import Component, SWMuxEntry, SWMuxEntryDimensioned
from components.field import Field
from . import templates
@ -184,23 +184,22 @@ class Register(Component):
f"{{{empty_bits}{{1'b{self.glbl_settings['rsvd_val']}}}}}")
# Create list of mux-inputs to later be picked up by carrying addrmap
# TODO: Create class
self.sw_mux_assignment_var_name.append(
(
self.process_yaml(
SWMuxEntry(
data_wire = self.process_yaml(
Register.templ_dict['sw_data_assignment_var_name'],
{'path': na_map[0],
'accesswidth': accesswidth}
),
self.process_yaml(
rdy_wire = self.process_yaml(
Register.templ_dict['sw_rdy_assignment_var_name'],
{'path': na_map[0]}
),
self.process_yaml(
err_wire = self.process_yaml(
Register.templ_dict['sw_err_assignment_var_name'],
{'path': na_map[0]}
),
f"{na_map[0]}_active", # Start addr
active_wire = f"{na_map[0]}_active",
)
)
@ -294,9 +293,9 @@ class Register(Component):
self.rtl_footer.append(
self.process_yaml(
Register.templ_dict['sw_data_assignment'],
{'sw_data_assignment_var_name': self.sw_mux_assignment_var_name[-1][0],
'sw_rdy_assignment_var_name': self.sw_mux_assignment_var_name[-1][1],
'sw_err_assignment_var_name': self.sw_mux_assignment_var_name[-1][2],
{'sw_data_assignment_var_name': self.sw_mux_assignment_var_name[-1].data_wire,
'sw_rdy_assignment_var_name': self.sw_mux_assignment_var_name[-1].rdy_wire,
'sw_err_assignment_var_name': self.sw_mux_assignment_var_name[-1].err_wire,
'genvars': self.genvars_str if not no_reads else '',
'rdy_condition': sw_rdy_condition,
'err_condition': sw_err_condition,
@ -305,25 +304,36 @@ class Register(Component):
)
def create_mux_string(self):
for mux_tuple in self.sw_mux_assignment_var_name:
for mux_entry in self.sw_mux_assignment_var_name:
# Loop through lowest dimension and add stride of higher
# dimension once everything is processed
if self.total_array_dimensions:
vec = [0]*len(self.total_array_dimensions)
for i in self.eval_genvars(vec, 0, self.total_array_dimensions):
yield (mux_tuple, i)
for dimension in Register.eval_genvars(vec, 0, self.total_array_dimensions):
yield (
SWMuxEntryDimensioned(
mux_entry = mux_entry,
dim = dimension
)
)
else:
yield(mux_tuple, '')
yield (
SWMuxEntryDimensioned(
mux_entry = mux_entry,
dim = ''
)
)
def eval_genvars(self, vec, depth, dimensions):
@staticmethod
def eval_genvars(vec, depth, dimensions):
for i in range(dimensions[depth]):
vec[depth] = i
if depth == len(dimensions) - 1:
yield '[{}]'.format(']['.join(map(str, vec)))
else:
yield from self.eval_genvars(vec, depth+1, dimensions)
yield from Register.eval_genvars(vec, depth+1, dimensions)
vec[depth] = 0

2
srdl2sv/components/templates/addrmap.yaml
View File

@ -135,7 +135,7 @@ default_mux_case:
end
list_of_mux_cases:
rtl: |-
{activate_wire}:
{active_wire}:
begin
r2b.data = {r2b_data};
r2b.err = {r2b_err};