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Do not generate seperate comparisons for cpu interface mux 

Rather, use the activate-signals that get generated anyway.
This commit is contained in:
Dennis Potter 2021-10-19 23:33:59 -07:00
parent 463bc22e12
commit d80224c43d
Signed by: Dennis
GPG Key ID: 186A8AD440942BAF
5 changed files with 29 additions and 43 deletions
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28
srdl2sv/components/addrmap.py
View File

@ -224,8 +224,7 @@ class AddrMap(Component):
#TODO: For optimal synthesis results, think about using 1B offsets rather than awkard 4B.
# for byte-access, byte-enables are used anyway
# Define default case
list_of_cases = [AddrMap.templ_dict['default_mux_case']['rtl']]
list_of_cases = []
# Add an entry for each version of a register
for child in self.children.values():
@ -235,30 +234,25 @@ class AddrMap(Component):
# [0] --> data_mux (str)
# [1] --> rdy_mux (str)
# [2] --> err_mux (str)
# [3] --> start_addr (int)
# mux_entry[1] --> offsets from start
# [0] --> Offset from start_addr of current entry (int)
# [1] --> String of array index that represents offset (str)
# [3] --> activate_wire (str)
# mux_entry[1] --> String of array index that represents offset (str)
r2b_data = ''.join([mux_entry[0][0], mux_entry[1][1]])
r2b_rdy = ''.join([mux_entry[0][1], mux_entry[1][1]])
r2b_err = ''.join([mux_entry[0][2], mux_entry[1][1]])
if child.__class__.__name__ == "Memory":
index = \
f"[{self.config['addrwidth']}'d{mux_entry[0][3][0]}:"\
f"{self.config['addrwidth']}'d{mux_entry[0][3][1]}]"
else:
index = f"{self.config['addrwidth']}'d{mux_entry[0][3] + mux_entry[1][0]}"
r2b_data = ''.join([mux_entry[0][0], mux_entry[1]])
r2b_rdy = ''.join([mux_entry[0][1], mux_entry[1]])
r2b_err = ''.join([mux_entry[0][2], mux_entry[1]])
activate_wire = ''.join([mux_entry[0][3], mux_entry[1]])
list_of_cases.append(
AddrMap.templ_dict['list_of_mux_cases']['rtl'].format(
index = index,
activate_wire = activate_wire,
r2b_data = r2b_data,
r2b_rdy = r2b_rdy,
r2b_err = r2b_err)
)
# Define default case
list_of_cases.append(AddrMap.templ_dict['default_mux_case']['rtl'])
self.rtl_footer.append(
self.process_yaml(
AddrMap.templ_dict['read_mux'],

17
srdl2sv/components/memory.py
View File

@ -108,9 +108,6 @@ class Memory(Component):
f"it is now defined as '{self.memwidth}'")
sys.exit(1)
# Geneate already started?
self.generate_active = glbl_settings['generate_active']
# Determine dimensions of register
if obj.is_array:
self.total_array_dimensions = [*parents_dimensions, *self.obj.array_dimensions]
@ -138,7 +135,7 @@ class Memory(Component):
def __add_sw_mux_assignments(self):
# Create list of mux-inputs to later be picked up by carrying addrmap
self.sw_mux_assignment_var_name = [
self.sw_mux_assignment_var_name = \
(
self.process_yaml(
Memory.templ_dict['sw_data_assignment_var_name'],
@ -153,9 +150,8 @@ class Memory(Component):
Memory.templ_dict['sw_err_assignment_var_name'],
{'path': self.path_underscored}
),
(self.obj.absolute_address, self.obj.absolute_address + self.obj.total_size)
f"{self.path_underscored}_mem_active"
)
]
if self.obj.get_property('sw') == AccessType.rw:
access_type = 'sw_data_assignment_rw'
@ -168,17 +164,16 @@ class Memory(Component):
self.process_yaml(
self.templ_dict[access_type],
{'path': self.path_underscored,
'sw_data_assignment_var_name': self.sw_mux_assignment_var_name[0][0],
'sw_rdy_assignment_var_name': self.sw_mux_assignment_var_name[0][1],
'sw_err_assignment_var_name': self.sw_mux_assignment_var_name[0][2],
'sw_data_assignment_var_name': self.sw_mux_assignment_var_name[0],
'sw_rdy_assignment_var_name': self.sw_mux_assignment_var_name[1],
'sw_err_assignment_var_name': self.sw_mux_assignment_var_name[2],
}
),
''
]
def create_mux_string(self):
for mux_tuple in self.sw_mux_assignment_var_name:
yield(mux_tuple, (0, ''))
yield(self.sw_mux_assignment_var_name, '')
def get_regwidth(self) -> int:
return self.memwidth

11
srdl2sv/components/register.py
View File

@ -184,6 +184,7 @@ class Register(Component):
f"{{{empty_bits}{{1'b{self.glbl_settings['rsvd_val']}}}}}")
# Create list of mux-inputs to later be picked up by carrying addrmap
# TODO: Create class
self.sw_mux_assignment_var_name.append(
(
self.process_yaml(
@ -199,7 +200,7 @@ class Register(Component):
Register.templ_dict['sw_err_assignment_var_name'],
{'path': na_map[0]}
),
na_map[1], # Start addr
f"{na_map[0]}_active", # Start addr
)
)
@ -313,21 +314,17 @@ class Register(Component):
for i in self.eval_genvars(vec, 0, self.total_array_dimensions):
yield (mux_tuple, i)
else:
yield(mux_tuple, (0, ''))
yield(mux_tuple, '')
def eval_genvars(self, vec, depth, dimensions):
for i in range(dimensions[depth]):
vec[depth] = i
if depth == len(dimensions) - 1:
yield (
eval(self.genvars_sum_str_vectorized),
'[{}]'.format(']['.join(map(str, vec)))
)
yield '[{}]'.format(']['.join(map(str, vec)))
else:
yield from self.eval_genvars(vec, depth+1, dimensions)
vec[depth] = 0
def __add_address_decoder(self):

4
srdl2sv/components/templates/addrmap.yaml
View File

@ -120,7 +120,7 @@ read_mux:
// Read multiplexer
always_comb
begin
case (b2r.addr) inside
unique case (1'b1)
{list_of_cases}
endcase
end
@ -135,7 +135,7 @@ default_mux_case:
end
list_of_mux_cases:
rtl: |-
{index}:
{activate_wire}:
begin
r2b.data = {r2b_data};
r2b.err = {r2b_err};

12
srdl2sv/components/templates/register.yaml
View File

@ -5,19 +5,19 @@ access_wire_comment:
// Register-activation for '{path}' {alias}
access_wire_assign_1_dim:
rtl: |-
assign {path}_accss = b2r.addr == {addr};
assign {path}_active = b2r.addr == {addr};
signals:
- name: '{path}_accss'
- name: '{path}_active'
signal_type: 'logic'
access_wire_assign_multi_dim:
rtl: |-
assign {path}_accss{genvars} = b2r.addr == {addr}+({genvars_sum});
assign {path}_active{genvars} = b2r.addr == {addr}+({genvars_sum});
signals:
- name: '{path}_accss'
- name: '{path}_active'
signal_type: 'logic'
read_wire_assign:
rtl: |-
assign {path}_sw_rd{genvars} = {path}_accss{genvars} && b2r.r_vld;
assign {path}_sw_rd{genvars} = {path}_active{genvars} && b2r.r_vld;
signals:
- name: '{path}_sw_rd'
signal_type: 'logic'
@ -29,7 +29,7 @@ read_wire_assign_0:
signal_type: 'logic'
write_wire_assign:
rtl: |-
assign {path}_sw_wr{genvars} = {path}_accss{genvars} && b2r.w_vld;
assign {path}_sw_wr{genvars} = {path}_active{genvars} && b2r.w_vld;
signals:
- name: '{path}_sw_wr'
signal_type: 'logic'