mirror of
https://github.com/Silicon1602/srdl2sv.git
synced 2024-12-22 06:58:41 +00:00
Do not generate seperate comparisons for cpu interface mux
Rather, use the activate-signals that get generated anyway.
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parent
463bc22e12
commit
d80224c43d
GPG Key ID:
186A8AD440942BAF
@ -224,8 +224,7 @@ class AddrMap(Component):
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#TODO: For optimal synthesis results, think about using 1B offsets rather than awkard 4B.
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# for byte-access, byte-enables are used anyway
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# Define default case
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list_of_cases = [AddrMap.templ_dict['default_mux_case']['rtl']]
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list_of_cases = []
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# Add an entry for each version of a register
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for child in self.children.values():
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@ -235,30 +234,25 @@ class AddrMap(Component):
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# [0] --> data_mux (str)
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# [1] --> rdy_mux (str)
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# [2] --> err_mux (str)
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# [3] --> start_addr (int)
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# mux_entry[1] --> offsets from start
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# [0] --> Offset from start_addr of current entry (int)
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# [1] --> String of array index that represents offset (str)
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# [3] --> activate_wire (str)
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# mux_entry[1] --> String of array index that represents offset (str)
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r2b_data = ''.join([mux_entry[0][0], mux_entry[1][1]])
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r2b_rdy = ''.join([mux_entry[0][1], mux_entry[1][1]])
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r2b_err = ''.join([mux_entry[0][2], mux_entry[1][1]])
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if child.__class__.__name__ == "Memory":
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index = \
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f"[{self.config['addrwidth']}'d{mux_entry[0][3][0]}:"\
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f"{self.config['addrwidth']}'d{mux_entry[0][3][1]}]"
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else:
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index = f"{self.config['addrwidth']}'d{mux_entry[0][3] + mux_entry[1][0]}"
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r2b_data = ''.join([mux_entry[0][0], mux_entry[1]])
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r2b_rdy = ''.join([mux_entry[0][1], mux_entry[1]])
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r2b_err = ''.join([mux_entry[0][2], mux_entry[1]])
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activate_wire = ''.join([mux_entry[0][3], mux_entry[1]])
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list_of_cases.append(
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AddrMap.templ_dict['list_of_mux_cases']['rtl'].format(
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index = index,
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activate_wire = activate_wire,
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r2b_data = r2b_data,
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r2b_rdy = r2b_rdy,
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r2b_err = r2b_err)
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)
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# Define default case
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list_of_cases.append(AddrMap.templ_dict['default_mux_case']['rtl'])
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self.rtl_footer.append(
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self.process_yaml(
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AddrMap.templ_dict['read_mux'],
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@ -108,9 +108,6 @@ class Memory(Component):
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f"it is now defined as '{self.memwidth}'")
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sys.exit(1)
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# Geneate already started?
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self.generate_active = glbl_settings['generate_active']
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# Determine dimensions of register
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if obj.is_array:
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self.total_array_dimensions = [*parents_dimensions, *self.obj.array_dimensions]
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@ -138,7 +135,7 @@ class Memory(Component):
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def __add_sw_mux_assignments(self):
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# Create list of mux-inputs to later be picked up by carrying addrmap
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self.sw_mux_assignment_var_name = [
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self.sw_mux_assignment_var_name = \
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(
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self.process_yaml(
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Memory.templ_dict['sw_data_assignment_var_name'],
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@ -153,9 +150,8 @@ class Memory(Component):
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Memory.templ_dict['sw_err_assignment_var_name'],
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{'path': self.path_underscored}
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),
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(self.obj.absolute_address, self.obj.absolute_address + self.obj.total_size)
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f"{self.path_underscored}_mem_active"
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)
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]
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if self.obj.get_property('sw') == AccessType.rw:
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access_type = 'sw_data_assignment_rw'
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@ -168,17 +164,16 @@ class Memory(Component):
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self.process_yaml(
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self.templ_dict[access_type],
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{'path': self.path_underscored,
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'sw_data_assignment_var_name': self.sw_mux_assignment_var_name[0][0],
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'sw_rdy_assignment_var_name': self.sw_mux_assignment_var_name[0][1],
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'sw_err_assignment_var_name': self.sw_mux_assignment_var_name[0][2],
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'sw_data_assignment_var_name': self.sw_mux_assignment_var_name[0],
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'sw_rdy_assignment_var_name': self.sw_mux_assignment_var_name[1],
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'sw_err_assignment_var_name': self.sw_mux_assignment_var_name[2],
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}
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),
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''
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]
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def create_mux_string(self):
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for mux_tuple in self.sw_mux_assignment_var_name:
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yield(mux_tuple, (0, ''))
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yield(self.sw_mux_assignment_var_name, '')
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def get_regwidth(self) -> int:
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return self.memwidth
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@ -184,6 +184,7 @@ class Register(Component):
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f"{{{empty_bits}{{1'b{self.glbl_settings['rsvd_val']}}}}}")
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# Create list of mux-inputs to later be picked up by carrying addrmap
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# TODO: Create class
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self.sw_mux_assignment_var_name.append(
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(
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self.process_yaml(
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@ -199,7 +200,7 @@ class Register(Component):
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Register.templ_dict['sw_err_assignment_var_name'],
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{'path': na_map[0]}
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),
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na_map[1], # Start addr
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f"{na_map[0]}_active", # Start addr
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)
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)
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@ -313,21 +314,17 @@ class Register(Component):
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for i in self.eval_genvars(vec, 0, self.total_array_dimensions):
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yield (mux_tuple, i)
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else:
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yield(mux_tuple, (0, ''))
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yield(mux_tuple, '')
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def eval_genvars(self, vec, depth, dimensions):
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for i in range(dimensions[depth]):
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vec[depth] = i
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if depth == len(dimensions) - 1:
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yield (
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eval(self.genvars_sum_str_vectorized),
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'[{}]'.format(']['.join(map(str, vec)))
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)
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yield '[{}]'.format(']['.join(map(str, vec)))
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else:
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yield from self.eval_genvars(vec, depth+1, dimensions)
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vec[depth] = 0
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def __add_address_decoder(self):
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@ -120,7 +120,7 @@ read_mux:
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// Read multiplexer
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always_comb
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begin
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case (b2r.addr) inside
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unique case (1'b1)
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{list_of_cases}
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endcase
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end
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@ -135,7 +135,7 @@ default_mux_case:
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end
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list_of_mux_cases:
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rtl: |-
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{index}:
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{activate_wire}:
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begin
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r2b.data = {r2b_data};
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r2b.err = {r2b_err};
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@ -5,19 +5,19 @@ access_wire_comment:
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// Register-activation for '{path}' {alias}
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access_wire_assign_1_dim:
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rtl: |-
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assign {path}_accss = b2r.addr == {addr};
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assign {path}_active = b2r.addr == {addr};
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signals:
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- name: '{path}_accss'
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- name: '{path}_active'
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signal_type: 'logic'
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access_wire_assign_multi_dim:
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rtl: |-
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assign {path}_accss{genvars} = b2r.addr == {addr}+({genvars_sum});
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assign {path}_active{genvars} = b2r.addr == {addr}+({genvars_sum});
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signals:
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- name: '{path}_accss'
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- name: '{path}_active'
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signal_type: 'logic'
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read_wire_assign:
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rtl: |-
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assign {path}_sw_rd{genvars} = {path}_accss{genvars} && b2r.r_vld;
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assign {path}_sw_rd{genvars} = {path}_active{genvars} && b2r.r_vld;
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signals:
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- name: '{path}_sw_rd'
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signal_type: 'logic'
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@ -29,7 +29,7 @@ read_wire_assign_0:
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signal_type: 'logic'
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write_wire_assign:
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rtl: |-
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assign {path}_sw_wr{genvars} = {path}_accss{genvars} && b2r.w_vld;
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assign {path}_sw_wr{genvars} = {path}_active{genvars} && b2r.w_vld;
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signals:
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- name: '{path}_sw_wr'
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signal_type: 'logic'
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