mirror of
https://github.com/Silicon1602/srdl2sv.git
synced 2025-04-19 13:02:57 +00:00
Dennis
32c6fc3c4a
Evaluating every single wire is maybe not the best way to do this, but it is probably better than writing a very exotic SV construct with (for-)loops, breaks, and a lot of conditions. Most synthesis tools are pretty good at recognizing this case-construct and generating a good mutliplexer.
64 lines
1.2 KiB
YAML
64 lines
1.2 KiB
YAML
---
|
|
module_declaration:
|
|
rtl: |-
|
|
module {name}
|
|
{import_package_list}
|
|
(
|
|
// Clock & Resets
|
|
input reg_clk,
|
|
input bus_clk,
|
|
input bus_rst_n,
|
|
{resets}
|
|
|
|
// Bus I/O
|
|
// TODO
|
|
|
|
// Inputs
|
|
{inputs}
|
|
|
|
// Outputs
|
|
{outputs}
|
|
);
|
|
import_package:
|
|
rtl: |-
|
|
import {name}_pkg::*
|
|
reset_port:
|
|
rtl:
|
|
input {name},
|
|
input_port:
|
|
rtl:
|
|
input {signal_type:{signal_width}} {name:{name_width}}{unpacked_dim},
|
|
output_port:
|
|
rtl:
|
|
output {signal_type:{signal_width}} {name:{name_width}}{unpacked_dim},
|
|
signal_declaration: |-
|
|
{type:{signal_width}} {name:{name_width}}{unpacked_dim};
|
|
package_declaration:
|
|
rtl: |-
|
|
package {name}_pkg;
|
|
|
|
{pkg_content}
|
|
|
|
endpackage
|
|
enum_declaration:
|
|
rtl: |-
|
|
typedef enum logic [{width}:0] {{
|
|
{enum_var_list}
|
|
}} {name};
|
|
enum_var_list_item:
|
|
rtl: |-
|
|
{name:{max_name_width}} = {width}'d{value}
|
|
read_mux:
|
|
rtl: |-
|
|
|
|
// Read multiplexer
|
|
always_comb
|
|
begin
|
|
case(addr)
|
|
{list_of_cases}
|
|
endcase
|
|
end
|
|
list_of_mux_cases:
|
|
rtl: |-
|
|
32'd{}: sw_rd_bus = {};
|