49 lines
1.3 KiB
Python
49 lines
1.3 KiB
Python
import yaml
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import re
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from systemrdl import RDLCompiler, RDLCompileError, RDLWalker, RDLListener, node
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from systemrdl.node import FieldNode
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# Local packages
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from components.register import Register
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from . import templates
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# Import templates
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try:
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import importlib.resources as pkg_resources
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except ImportError:
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# Try backported to PY<37 `importlib_resources`.
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import importlib_resources as pkg_resources
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class AddrMap:
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def __init__(self, rdlc: RDLCompiler, obj: node.RootNode):
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self.rdlc = rdlc
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template = pkg_resources.read_text(templates, 'addrmap.sv')
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# Read template for SystemVerilog module
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tmpl_addrmap = re.compile("{addrmap_name}")
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self.rtl = tmpl_addrmap.sub(obj.inst_name, template)
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# Empty list of register logic
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self.registers = set()
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# Traverse through children
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for child in obj.children():
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if isinstance(child, node.AddrmapNode):
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pass
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elif isinstance(child, node.RegfileNode):
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pass
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elif isinstance(child, node.RegNode):
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self.registers.add(Register(child))
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for i in self.registers:
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print("\n\n")
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for j in i.rtl:
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print(j)
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def get_rtl(self) -> str:
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return '\n'.join(self.rtl)
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