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A SystemRDL 2.0 to (synthesizable) SystemVerilog compiler.
1 Commit 1 Branch 0 Tags 713 KiB
Python 92.9%
SystemVerilog 5.7%
Makefile 1.4%
861a020aff
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Dennis 861a020aff
Initial commit of SRDL2SV 
The compiler in this commit is still useless and only contains a
very rough skeleton of the code. SRDL2SV is only able to
create a simple register with hw=rw/sw=rw fields.
2021-05-02 00:58:43 +02:00
srdl2sv Initial commit of SRDL2SV 2021-05-02 00:58:43 +02:00
.gitignore Initial commit of SRDL2SV 2021-05-02 00:58:43 +02:00
LIMITATIONS.md Initial commit of SRDL2SV 2021-05-02 00:58:43 +02:00