21 lines
819 B
YAML
21 lines
819 B
YAML
---
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rw_wire_declare: |
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logic {name}_wr {depth};
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logic {name}_rd {depth};
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rw_wire_assign: |
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assign {name}_bus_wr[i] = addr == {} && r_vld;
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assign {name}_bus_wr[i] = addr == {} && r_vld;
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reg_comment: |-
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/*******************************************************************
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*******************************************************************
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* REGISTER : {name}
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* DIMENSION : {dimensions}
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* DEPTHS (per dimension): {depth}
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*******************************************************************
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*******************************************************************/
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generate_for_start: |-
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{indent}for ({iterator} = 0; {iterator} < {limit}; {iterator}++)
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{indent}begin
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generate_for_end: |-
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{indent}end // of for loop with iterator {dimension}
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