mirror of
https://github.com/Silicon1602/srdl2sv.git
synced 2025-04-19 13:02:57 +00:00
Dennis
8a82d37737
Apart from adding regfiles in general (which is mostly a combination of addrmap and register code), the stride/array_dimension code had to be revisted to be correct for multi dimensional arrays with multi dimensional registers. Lastly, the logger instantiation has been moved to the __init__() method of `Component`.
183 lines
6.2 KiB
Python
183 lines
6.2 KiB
Python
import importlib.resources as pkg_resources
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import yaml
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import math
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from systemrdl import node
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# Local modules
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from components.component import Component
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from components.field import Field
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from . import templates
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class Register(Component):
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# Save YAML template as class variable
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templ_dict = yaml.load(
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pkg_resources.read_text(templates, 'regs.yaml'),
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Loader=yaml.FullLoader)
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def __init__(
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self,
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obj: node.RegNode,
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parents_dimensions: list,
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parents_stride: list,
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config: dict,
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glbl_settings: dict):
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super().__init__(obj, config)
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# Save and/or process important variables
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self.__process_variables(obj, parents_dimensions, parents_stride)
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# Create RTL for fields
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# Fields should be in order in RTL,therefore, use list
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for field in obj.fields():
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field_obj = Field(field, self.total_array_dimensions, config, glbl_settings)
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if not config['disable_sanity']:
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field_obj.sanity_checks()
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self.children.append(field_obj)
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# Create generate block for register and add comment
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if self.dimensions:
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self.rtl_header.append("generate")
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for i in range(self.dimensions):
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self.rtl_header.append(
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Register.templ_dict['generate_for_start'].format(
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iterator = chr(97+i+self.parents_depths),
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limit = self.array_dimensions[i]))
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# End loops
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for i in range(self.dimensions-1, -1, -1):
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self.rtl_footer.append(
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Register.templ_dict['generate_for_end'].format(
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dimension = chr(97+i)))
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if self.dimensions:
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self.rtl_footer.append("endgenerate")
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# Assign variables from bus
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self.obj.current_idx = [0]
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if self.dimensions:
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rw_wire_assign_field = 'rw_wire_assign_multi_dim'
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else:
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rw_wire_assign_field = 'rw_wire_assign_1_dim'
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self.rtl_header.append(
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Register.templ_dict[rw_wire_assign_field]['rtl'].format(
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path = self.path_underscored,
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addr = self.obj.absolute_address,
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genvars = self.genvars_str,
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genvars_sum =self.genvars_sum_str,
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depth = self.depth))
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self.yaml_signals_to_list(Register.templ_dict[rw_wire_assign_field])
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# Add wire/register instantiations
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dict_list = [(key, value) for (key, value) in self.get_signals().items()]
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signal_width = min(max([len(value[0]) for (_, value) in dict_list]), 40)
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name_width = min(max([len(key) for (key, _) in dict_list]), 40)
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self.rtl_header = [
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*[
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Register.templ_dict['signal_declaration'].format(
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name = key,
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type = value[0],
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signal_width = signal_width,
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name_width = name_width,
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unpacked_dim = '[{}]'.format(
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']['.join(
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[str(y) for y in value[1]]))
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if value[1] else '')
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for (key, value) in dict_list],
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'',
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*self.rtl_header,
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]
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# Create comment and provide user information about register he/she
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# is looking at.
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self.rtl_header = [
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Register.templ_dict['reg_comment'].format(
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name = obj.inst_name,
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dimensions = self.dimensions,
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depth = self.depth),
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*self.rtl_header
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]
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def __process_variables(
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self,
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obj: node.RegNode,
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parents_dimensions: list,
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parents_stride: list):
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# Save object
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self.obj = obj
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# Save name
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self.name = obj.inst_name
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# Create full name
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self.create_underscored_path()
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# Determine dimensions of register
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if obj.is_array:
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self.sel_arr = 'array'
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self.total_array_dimensions = [*parents_dimensions, *self.obj.array_dimensions]
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self.array_dimensions = self.obj.array_dimensions
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# Merge parent's stride with stride of this regfile. Before doing so, the
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# respective stride of the different dimensions shall be calculated
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self.total_stride = [
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*parents_stride,
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*[math.prod(self.array_dimensions[i+1:])
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*self.obj.array_stride
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for i, _ in enumerate(self.array_dimensions)]
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]
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else:
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self.sel_arr = 'single'
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self.total_array_dimensions = parents_dimensions
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self.array_dimensions = []
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self.total_stride = self.obj.array_stride
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# How many dimensions were already part of some higher up hierarchy?
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self.parents_depths = len(parents_dimensions)
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self.total_depth = '[{}]'.format(']['.join(f"{i}" for i in self.total_array_dimensions))
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self.total_dimensions = len(self.total_array_dimensions)
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self.depth = '[{}]'.format(']['.join(f"{i}" for i in self.array_dimensions))
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self.dimensions = len(self.array_dimensions)
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# Calculate how many genvars shall be added
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genvars = ['[{}]'.format(chr(97+i)) for i in range(self.total_dimensions)]
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self.genvars_str = ''.join(genvars)
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# Determine value to compare address with
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genvars_sum = []
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try:
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for i, stride in enumerate(self.total_stride):
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genvars_sum.append(chr(97+i))
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genvars_sum.append("*")
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genvars_sum.append(str(stride))
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genvars_sum.append("+")
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genvars_sum.pop()
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self.logger.debug(
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"Multidimensional with dimensions '{}' and stride '{}'".format(
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self.total_array_dimensions,
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self.total_stride))
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except TypeError:
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self.logger.debug(
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"Caught expected TypeError because self.total_stride is empty")
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except IndexError:
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self.logger.debug(
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"Caugt expected IndexError because genvars_sum is empty")
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self.genvars_sum_str = ''.join(genvars_sum)
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