srdl2sv

mirror of https://github.com/Silicon1602/srdl2sv.git synced 2024-12-22 06:58:41 +00:00

A SystemRDL 2.0 to (synthesizable) SystemVerilog compiler.

asic fpga hardware-description-language hdl rdl register-description-language registers systemrdl systemrdl-compiler systemverilog verilog

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Dennis 8a82d37737 Add regfile capabilities Apart from adding regfiles in general (which is mostly a combination of addrmap and register code), the stride/array_dimension code had to be revisted to be correct for multi dimensional arrays with multi dimensional registers. Lastly, the logger instantiation has been moved to the __init__() method of `Component`.	2021-05-31 00:37:41 +02:00
srdl2sv	Add regfile capabilities	2021-05-31 00:37:41 +02:00
.gitignore	Initial commit of SRDL2SV	2021-05-02 00:58:43 +02:00
LIMITATIONS.md	Initial commit of SRDL2SV	2021-05-02 00:58:43 +02:00

Dennis 8a82d37737

Add regfile capabilities

Apart from adding regfiles in general (which is mostly a combination of
addrmap and register code), the stride/array_dimension code had to be
revisted to be correct for multi dimensional arrays with multi
dimensional registers.

Lastly, the logger instantiation has been moved to the __init__()
method of `Component`.

2021-05-31 00:37:41 +02:00

srdl2sv

Add regfile capabilities

2021-05-31 00:37:41 +02:00

.gitignore

Initial commit of SRDL2SV

2021-05-02 00:58:43 +02:00

LIMITATIONS.md

Initial commit of SRDL2SV

2021-05-02 00:58:43 +02:00