534 lines
20 KiB
Systemverilog
534 lines
20 KiB
Systemverilog
/*****************************************************************
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*
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* ███████╗██████╗ ██████╗ ██╗ ██████╗ ███████╗██╗ ██╗
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* ██╔════╝██╔══██╗██╔══██╗██║ ╚════██╗██╔════╝██║ ██║
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* ███████╗██████╔╝██║ ██║██║ █████╔╝███████╗██║ ██║
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* ╚════██║██╔══██╗██║ ██║██║ ██╔═══╝ ╚════██║╚██╗ ██╔╝
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* ███████║██║ ██║██████╔╝███████╗███████╗███████║ ╚████╔╝
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* ╚══════╝╚═╝ ╚═╝╚═════╝ ╚══════╝╚══════╝╚══════╝ ╚═══╝
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*
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* The present RTL was generated by srdl2sv v0.01. The RTL and all
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* templates the RTL is derived from are licensed under the MIT
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* license. The license is shown below.
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*
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* srdl2sv itself is licensed under GPLv3.
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*
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* Maintainer : Dennis Potter <dennis@dennispotter.eu>
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* Report Bugs: https://github.com/Silicon1602/srdl2sv/issues
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*
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* ===GENERATION INFORMATION======================================
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*
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* Generation information:
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* - User: : dpotter
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* - Time : November 26 2021 16:52:16
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* - Path : /home/dpotter/srdl2sv/examples/simple_rw_reg
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* - RDL file : ['simple_rw_reg.rdl']
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* - Hostname : ArchXPS
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*
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* RDL include directories:
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* -
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*
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* Commandline arguments to srdl2sv:
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* - Ouput Directory : srdl2sv_out
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* - Stream Log Level : INFO
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* - File Log Level : NONE
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* - Use Real Tabs : False
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* - Tab Width : 4
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* - Enums Enabled : True
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* - Address Errors : True
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* - Unpacked I/Os : True
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* - Register Bus Type: amba3ahblite
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* - Address width : 32
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* - Byte enables : True
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* - Descriptions : {'AddrMap': False, 'RegFile': False, 'Memory': False, 'Register': False, 'Field': False}
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*
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* ===LICENSE OF SIMPLE_RW_REG.SV=====================================
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*
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* Copyright 2021 Dennis Potter <dennis@dennispotter.eu>
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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****************************************************************/
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module simple_rw_reg
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(
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// Reset signals declared for registers
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input async_rst_n,
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input sync_rst_n,
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// Ports for 'General Clock'
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input clk,
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// Ports for 'AHB Protocol'
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input HRESETn ,
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input [31:0] HADDR ,
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input HWRITE ,
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input [2:0] HSIZE ,
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input [3:0] HPROT ,
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input [1:0] HTRANS ,
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input [32-1:0] HWDATA ,
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input HSEL ,
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output HREADYOUT,
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output HRESP ,
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output [32-1:0] HRDATA ,
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// Ports for 'register_1d'
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input register_1d__f1_hw_wr,
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input [15:0] register_1d__f1_in ,
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output [15:0] register_1d__f1_r ,
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input register_1d__f2_hw_wr,
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input [15:0] register_1d__f2_in ,
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output [15:0] register_1d__f2_r ,
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// Ports for 'register_2d'
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input register_2d__f1_hw_wr[2],
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input [15:0] register_2d__f1_in [2],
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output [15:0] register_2d__f1_r [2],
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input register_2d__f2_hw_wr[2],
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input [15:0] register_2d__f2_in [2],
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output [15:0] register_2d__f2_r [2],
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// Ports for 'register_3d'
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input register_3d__f1_hw_wr[2][2],
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input [15:0] register_3d__f1_in [2][2],
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output [15:0] register_3d__f1_r [2][2],
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input register_3d__f2_hw_wr[2][2],
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input [15:0] register_3d__f2_in [2][2],
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output [15:0] register_3d__f2_r [2][2]
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);
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// Internal signals
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srdl2sv_widget_if #(.ADDR_W (32), .DATA_W(32)) widget_if;
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/*******************************************************************
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* AMBA 3 AHB Lite Widget
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* ======================
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* Naming conventions
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* - widget_if -> SystemVerilog interface to between widgets
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* and the internal srdl2sv registers.
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* - H* -> Signals as defined in AMBA3 AHB Lite
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* specification
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* - clk -> Clock that drives registers and the bus
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*******************************************************************/
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srdl2sv_amba3ahblite
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#(.FLOP_REGISTER_IF (0),
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.BUS_BITS (32),
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.NO_BYTE_ENABLE (0))
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srdl2sv_amba3ahblite_inst
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(// Bus protocol
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.HRESETn,
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.HCLK (clk),
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.HADDR,
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.HWRITE,
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.HSIZE,
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.HPROT,
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.HTRANS,
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.HWDATA,
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.HSEL,
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.HREADYOUT,
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.HRESP,
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.HRDATA,
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// Interface to internal logic
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.widget_if);
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genvar gv_a, gv_b;
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/*******************************************************************
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/*******************************************************************
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/* REGISTER : register_1d
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/* DIMENSION : 0
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/* DEPTHS (per dimension): []
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/*******************************************************************
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/*******************************************************************/
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logic register_1d_active ;
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logic register_1d_sw_wr ;
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logic [31:0] register_1d_data_mux_in;
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logic register_1d_rdy_mux_in ;
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logic register_1d_err_mux_in ;
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logic [15:0] register_1d__f1_q ;
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logic [15:0] register_1d__f2_q ;
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// Register-activation for 'register_1d'
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assign register_1d_active = widget_if.addr == 0;
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assign register_1d_sw_wr = register_1d_active && widget_if.w_vld;
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//-----------------FIELD SUMMARY-----------------
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// name : f1 (register_1d[15:0])
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// access : hw = rw
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// sw = rw (precedence)
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// reset : - / -
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// flags : ['sw', 'we']
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// external : False
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// storage type : StorageType.FLOPS
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//-----------------------------------------------
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always_ff @(posedge clk)
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begin
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if (register_1d_sw_wr)
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begin
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if (widget_if.byte_en[0])
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register_1d__f1_q[7:0] <= widget_if.w_data[7:0];
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if (widget_if.byte_en[1])
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register_1d__f1_q[15:8] <= widget_if.w_data[15:8];
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end
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else
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if (register_1d__f1_hw_wr)
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register_1d__f1_q <= register_1d__f1_in;
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end // of register_1d__f1's always_ff
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// Connect register to hardware output port
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assign register_1d__f1_r = register_1d__f1_q;
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//-----------------FIELD SUMMARY-----------------
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// name : f2 (register_1d[31:16])
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// access : hw = rw
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// sw = rw (precedence)
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// reset : - / -
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// flags : ['sw', 'we']
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// external : False
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// storage type : StorageType.FLOPS
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//-----------------------------------------------
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always_ff @(posedge clk)
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begin
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if (register_1d_sw_wr)
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begin
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if (widget_if.byte_en[2])
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register_1d__f2_q[7:0] <= widget_if.w_data[23:16];
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if (widget_if.byte_en[3])
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register_1d__f2_q[15:8] <= widget_if.w_data[31:24];
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end
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else
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if (register_1d__f2_hw_wr)
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register_1d__f2_q <= register_1d__f2_in;
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end // of register_1d__f2's always_ff
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// Connect register to hardware output port
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assign register_1d__f2_r = register_1d__f2_q;
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/**********************************************
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* Assign all fields to signal to Mux *
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**********************************************/
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// Assign all fields. Fields that are not readable are tied to 0.
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assign register_1d_data_mux_in = {register_1d__f2_q, register_1d__f1_q};
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// Internal registers are ready immediately
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assign register_1d_rdy_mux_in = 1'b1;
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// Return an error if *no* read and *no* write was succesful. If some bits
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// cannot be read/written but others are succesful, don't return and error
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// Hence, as long as one action can be succesful, no error will be returned.
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assign register_1d_err_mux_in = !((widget_if.r_vld && (|widget_if.byte_en[3:0])) || (widget_if.w_vld && (|widget_if.byte_en[3:0])));
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/*******************************************************************
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/*******************************************************************
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/* REGISTER : register_2d
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/* DIMENSION : 1
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/* DEPTHS (per dimension): [2]
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/*******************************************************************
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/*******************************************************************/
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logic register_2d_active [2];
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logic register_2d_sw_wr [2];
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logic [31:0] register_2d_data_mux_in[2];
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logic register_2d_rdy_mux_in [2];
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logic register_2d_err_mux_in [2];
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logic [15:0] register_2d__f1_q [2];
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logic [15:0] register_2d__f2_q [2];
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generate
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for (gv_a = 0; gv_a < 2; gv_a++)
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begin
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// Register-activation for 'register_2d'
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assign register_2d_active[gv_a] = widget_if.addr == 4+(gv_a*4);
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assign register_2d_sw_wr[gv_a] = register_2d_active[gv_a] && widget_if.w_vld;
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//-----------------FIELD SUMMARY-----------------
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// name : f1 (register_2d[15:0])
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// access : hw = rw
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// sw = rw (precedence)
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// reset : active_low / asynchronous
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// flags : ['sw', 'we', 'resetsignal']
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// external : False
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// storage type : StorageType.FLOPS
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//-----------------------------------------------
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always_ff @(posedge clk or negedge async_rst_n)
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if (!async_rst_n)
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begin
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register_2d__f1_q[gv_a] <= 16'd0;
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end
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else
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begin
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if (register_2d_sw_wr[gv_a])
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begin
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if (widget_if.byte_en[0])
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register_2d__f1_q[gv_a][7:0] <= widget_if.w_data[7:0];
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if (widget_if.byte_en[1])
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register_2d__f1_q[gv_a][15:8] <= widget_if.w_data[15:8];
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end
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else
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if (register_2d__f1_hw_wr[gv_a])
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register_2d__f1_q[gv_a] <= register_2d__f1_in[gv_a];
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end // of register_2d__f1's always_ff
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// Connect register to hardware output port
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assign register_2d__f1_r[gv_a] = register_2d__f1_q[gv_a];
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//-----------------FIELD SUMMARY-----------------
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// name : f2 (register_2d[31:16])
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// access : hw = rw
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// sw = rw (precedence)
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// reset : active_low / asynchronous
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// flags : ['sw', 'we', 'resetsignal']
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// external : False
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// storage type : StorageType.FLOPS
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//-----------------------------------------------
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always_ff @(posedge clk or negedge async_rst_n)
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if (!async_rst_n)
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begin
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register_2d__f2_q[gv_a] <= 16'dx;
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end
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else
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begin
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if (register_2d_sw_wr[gv_a])
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begin
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if (widget_if.byte_en[2])
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register_2d__f2_q[gv_a][7:0] <= widget_if.w_data[23:16];
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if (widget_if.byte_en[3])
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register_2d__f2_q[gv_a][15:8] <= widget_if.w_data[31:24];
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end
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else
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if (register_2d__f2_hw_wr[gv_a])
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register_2d__f2_q[gv_a] <= register_2d__f2_in[gv_a];
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end // of register_2d__f2's always_ff
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// Connect register to hardware output port
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assign register_2d__f2_r[gv_a] = register_2d__f2_q[gv_a];
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/**********************************************
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* Assign all fields to signal to Mux *
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**********************************************/
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// Assign all fields. Fields that are not readable are tied to 0.
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assign register_2d_data_mux_in[gv_a] = {register_2d__f2_q[gv_a], register_2d__f1_q[gv_a]};
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// Internal registers are ready immediately
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assign register_2d_rdy_mux_in[gv_a] = 1'b1;
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// Return an error if *no* read and *no* write was succesful. If some bits
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// cannot be read/written but others are succesful, don't return and error
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// Hence, as long as one action can be succesful, no error will be returned.
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assign register_2d_err_mux_in[gv_a] = !((widget_if.r_vld && (|widget_if.byte_en[3:0])) || (widget_if.w_vld && (|widget_if.byte_en[3:0])));
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end // of for loop with iterator gv_a
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endgenerate
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/*******************************************************************
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/*******************************************************************
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/* REGISTER : register_3d
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/* DIMENSION : 2
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/* DEPTHS (per dimension): [2][2]
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/*******************************************************************
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/*******************************************************************/
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logic register_3d_active [2][2];
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logic register_3d_sw_wr [2][2];
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logic [31:0] register_3d_data_mux_in[2][2];
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logic register_3d_rdy_mux_in [2][2];
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logic register_3d_err_mux_in [2][2];
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logic [15:0] register_3d__f1_q [2][2];
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logic [15:0] register_3d__f2_q [2][2];
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generate
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for (gv_a = 0; gv_a < 2; gv_a++)
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begin
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for (gv_b = 0; gv_b < 2; gv_b++)
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begin
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// Register-activation for 'register_3d'
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assign register_3d_active[gv_a][gv_b] = widget_if.addr == 12+(gv_a*8+gv_b*4);
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assign register_3d_sw_wr[gv_a][gv_b] = register_3d_active[gv_a][gv_b] && widget_if.w_vld;
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//-----------------FIELD SUMMARY-----------------
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// name : f1 (register_3d[15:0])
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// access : hw = rw
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// sw = rw (precedence)
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// reset : active_high / synchronous
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// flags : ['sw', 'we', 'resetsignal']
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// external : False
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// storage type : StorageType.FLOPS
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//-----------------------------------------------
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always_ff @(posedge clk)
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if (sync_rst_n)
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begin
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register_3d__f1_q[gv_a][gv_b] <= 16'd0;
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end
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else
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begin
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if (register_3d_sw_wr[gv_a][gv_b])
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begin
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if (widget_if.byte_en[0])
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register_3d__f1_q[gv_a][gv_b][7:0] <= widget_if.w_data[7:0];
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if (widget_if.byte_en[1])
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register_3d__f1_q[gv_a][gv_b][15:8] <= widget_if.w_data[15:8];
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end
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else
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if (register_3d__f1_hw_wr[gv_a][gv_b])
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register_3d__f1_q[gv_a][gv_b] <= register_3d__f1_in[gv_a][gv_b];
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end // of register_3d__f1's always_ff
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// Connect register to hardware output port
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assign register_3d__f1_r[gv_a][gv_b] = register_3d__f1_q[gv_a][gv_b];
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//-----------------FIELD SUMMARY-----------------
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// name : f2 (register_3d[31:16])
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// access : hw = rw
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// sw = rw (precedence)
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// reset : active_high / synchronous
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// flags : ['sw', 'we', 'resetsignal']
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// external : False
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// storage type : StorageType.FLOPS
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//-----------------------------------------------
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always_ff @(posedge clk)
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if (sync_rst_n)
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begin
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register_3d__f2_q[gv_a][gv_b] <= 16'dx;
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end
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else
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begin
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if (register_3d_sw_wr[gv_a][gv_b])
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begin
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if (widget_if.byte_en[2])
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register_3d__f2_q[gv_a][gv_b][7:0] <= widget_if.w_data[23:16];
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if (widget_if.byte_en[3])
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register_3d__f2_q[gv_a][gv_b][15:8] <= widget_if.w_data[31:24];
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end
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else
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if (register_3d__f2_hw_wr[gv_a][gv_b])
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register_3d__f2_q[gv_a][gv_b] <= register_3d__f2_in[gv_a][gv_b];
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end // of register_3d__f2's always_ff
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// Connect register to hardware output port
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assign register_3d__f2_r[gv_a][gv_b] = register_3d__f2_q[gv_a][gv_b];
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|
|
|
|
|
|
|
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/**********************************************
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|
* Assign all fields to signal to Mux *
|
|
**********************************************/
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// Assign all fields. Fields that are not readable are tied to 0.
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assign register_3d_data_mux_in[gv_a][gv_b] = {register_3d__f2_q[gv_a][gv_b], register_3d__f1_q[gv_a][gv_b]};
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|
|
|
// Internal registers are ready immediately
|
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assign register_3d_rdy_mux_in[gv_a][gv_b] = 1'b1;
|
|
|
|
// Return an error if *no* read and *no* write was succesful. If some bits
|
|
// cannot be read/written but others are succesful, don't return and error
|
|
// Hence, as long as one action can be succesful, no error will be returned.
|
|
assign register_3d_err_mux_in[gv_a][gv_b] = !((widget_if.r_vld && (|widget_if.byte_en[3:0])) || (widget_if.w_vld && (|widget_if.byte_en[3:0])));
|
|
end // of for loop with iterator gv_b
|
|
end // of for loop with iterator gv_a
|
|
|
|
endgenerate
|
|
|
|
|
|
// Read multiplexer
|
|
always_comb
|
|
begin
|
|
unique case (1'b1)
|
|
register_1d_active:
|
|
begin
|
|
widget_if.r_data = register_1d_data_mux_in;
|
|
widget_if.err = register_1d_err_mux_in;
|
|
widget_if.rdy = register_1d_rdy_mux_in;
|
|
end
|
|
register_2d_active[0]:
|
|
begin
|
|
widget_if.r_data = register_2d_data_mux_in[0];
|
|
widget_if.err = register_2d_err_mux_in[0];
|
|
widget_if.rdy = register_2d_rdy_mux_in[0];
|
|
end
|
|
register_2d_active[1]:
|
|
begin
|
|
widget_if.r_data = register_2d_data_mux_in[1];
|
|
widget_if.err = register_2d_err_mux_in[1];
|
|
widget_if.rdy = register_2d_rdy_mux_in[1];
|
|
end
|
|
register_3d_active[0][0]:
|
|
begin
|
|
widget_if.r_data = register_3d_data_mux_in[0][0];
|
|
widget_if.err = register_3d_err_mux_in[0][0];
|
|
widget_if.rdy = register_3d_rdy_mux_in[0][0];
|
|
end
|
|
register_3d_active[0][1]:
|
|
begin
|
|
widget_if.r_data = register_3d_data_mux_in[0][1];
|
|
widget_if.err = register_3d_err_mux_in[0][1];
|
|
widget_if.rdy = register_3d_rdy_mux_in[0][1];
|
|
end
|
|
register_3d_active[1][0]:
|
|
begin
|
|
widget_if.r_data = register_3d_data_mux_in[1][0];
|
|
widget_if.err = register_3d_err_mux_in[1][0];
|
|
widget_if.rdy = register_3d_rdy_mux_in[1][0];
|
|
end
|
|
register_3d_active[1][1]:
|
|
begin
|
|
widget_if.r_data = register_3d_data_mux_in[1][1];
|
|
widget_if.err = register_3d_err_mux_in[1][1];
|
|
widget_if.rdy = register_3d_rdy_mux_in[1][1];
|
|
end
|
|
default:
|
|
begin
|
|
// If the address is not found, return an error
|
|
widget_if.r_data = 0;
|
|
widget_if.err = 1;
|
|
widget_if.rdy = widget_if.r_vld || widget_if.w_vld;
|
|
end
|
|
endcase
|
|
end
|
|
endmodule
|