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Add simple_rw_reg example with reset signals

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This commit is contained in:
Dennis Potter 2021-11-26 16:53:06 -08:00
parent d8add0d5f2
commit 9cb53f0fb0
Signed by: Dennis
GPG Key ID: 186A8AD440942BAF
2 changed files with 56 additions and 15 deletions
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26
examples/simple_rw_reg/simple_rw_reg.rdl
View File

@ -2,26 +2,46 @@
// - A 1-dimensional register
// - A 2-dimensional register
// - A 3-dimensional register
//
// Note that no reset is defined, so none of the registers will be
// resetable.
// Not defined as field_reset!
signal {activelow; async;} async_rst_n;
signal {activehigh; sync;} sync_rst_n;
addrmap simple_rw_reg {
// 1-D register
reg {
desc = "None of the fields in this register have a reset";
field {sw=rw; hw=rw; we;} f1 [15:0];
field {sw=rw; hw=rw; we;} f2 [31:16];
} register_1d;
// 2-D register
reg {
desc = "Both fields are connected to a reset signal, but
only one field actually gets a reset value.";
field {sw=rw; hw=rw; we;} f1 [15:0];
field {sw=rw; hw=rw; we;} f2 [31:16];
f1->resetsignal = async_rst_n;
f2->resetsignal = async_rst_n;
f1->reset = 0;
} register_2d[2];
// 3-D register
reg {
desc = "Similar to register_2d, but now the resets are
reset synchronously.";
field {sw=rw; hw=rw; we;} f1 [15:0];
field {sw=rw; hw=rw; we;} f2 [31:16];
f1->resetsignal = sync_rst_n;
f2->resetsignal = sync_rst_n;
f1->reset = 0;
// Show what happens if a field is not reset
} register_3d[2][2];
};

45
examples/simple_rw_reg/srdl2sv_out/simple_rw_reg.sv
View File

@ -20,7 +20,7 @@
*
* Generation information:
* - User: : dpotter
* - Time : November 26 2021 16:32:58
* - Time : November 26 2021 16:52:16
* - Path : /home/dpotter/srdl2sv/examples/simple_rw_reg
* - RDL file : ['simple_rw_reg.rdl']
* - Hostname : ArchXPS
@ -71,7 +71,8 @@ module simple_rw_reg
(
// Reset signals declared for registers
input async_rst_n,
input sync_rst_n,
// Ports for 'General Clock'
input clk,
@ -277,13 +278,18 @@ begin
// name : f1 (register_2d[15:0])
// access : hw = rw
// sw = rw (precedence)
// reset : - / -
// flags : ['sw', 'we']
// reset : active_low / asynchronous
// flags : ['sw', 'we', 'resetsignal']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk)
always_ff @(posedge clk or negedge async_rst_n)
if (!async_rst_n)
begin
register_2d__f1_q[gv_a] <= 16'd0;
end
else
begin
if (register_2d_sw_wr[gv_a])
begin
@ -306,13 +312,18 @@ begin
// name : f2 (register_2d[31:16])
// access : hw = rw
// sw = rw (precedence)
// reset : - / -
// flags : ['sw', 'we']
// reset : active_low / asynchronous
// flags : ['sw', 'we', 'resetsignal']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk)
always_ff @(posedge clk or negedge async_rst_n)
if (!async_rst_n)
begin
register_2d__f2_q[gv_a] <= 16'dx;
end
else
begin
if (register_2d_sw_wr[gv_a])
begin
@ -380,13 +391,18 @@ begin
// name : f1 (register_3d[15:0])
// access : hw = rw
// sw = rw (precedence)
// reset : - / -
// flags : ['sw', 'we']
// reset : active_high / synchronous
// flags : ['sw', 'we', 'resetsignal']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk)
if (sync_rst_n)
begin
register_3d__f1_q[gv_a][gv_b] <= 16'd0;
end
else
begin
if (register_3d_sw_wr[gv_a][gv_b])
begin
@ -409,13 +425,18 @@ begin
// name : f2 (register_3d[31:16])
// access : hw = rw
// sw = rw (precedence)
// reset : - / -
// flags : ['sw', 'we']
// reset : active_high / synchronous
// flags : ['sw', 'we', 'resetsignal']
// external : False
// storage type : StorageType.FLOPS
//-----------------------------------------------
always_ff @(posedge clk)
if (sync_rst_n)
begin
register_3d__f2_q[gv_a][gv_b] <= 16'dx;
end
else
begin
if (register_3d_sw_wr[gv_a][gv_b])
begin