mirror of
https://github.com/Silicon1602/srdl2sv.git
synced 2025-07-08 00:32:23 +00:00
Dennis
c689190080
The error indication is generated if:
- A non-existent register gets read
- An existent register gets read but not a single bit can be
succesfully read or written. As soon as 1 bit succeeds don't
return an error.
18 lines
281 B
Systemverilog
18 lines
281 B
Systemverilog
package srdl2sv_widget_pkg;
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typedef struct {
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logic [31:0] addr;
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logic [31:0] data;
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logic w_vld;
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logic r_vld;
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logic [ 3:0] byte_en;
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} b2r_t;
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typedef struct {
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logic [31:0] data;
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logic rdy;
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logic err;
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} r2b_t;
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endpackage
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