srdl2sv

mirror of https://github.com/Silicon1602/srdl2sv.git synced 2024-11-13 02:53:37 +00:00

A SystemRDL 2.0 to (synthesizable) SystemVerilog compiler.

asic fpga hardware-description-language hdl rdl register-description-language registers systemrdl systemrdl-compiler systemverilog verilog

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Dennis b7c1a12179 Add support for enumeration encoding Fields that are encoded as enumerations are now recognized by the application. All relevant information will be saved in the Field Object and the variables and I/O list will be generated accordingly. This commit also adds dynamic padding of the I/O and variable lists. Still lacking is the automatic generation of SV packages.	2021-05-24 11:41:45 +02:00
srdl2sv	Add support for enumeration encoding	2021-05-24 11:41:45 +02:00
.gitignore	Initial commit of SRDL2SV	2021-05-02 00:58:43 +02:00
LIMITATIONS.md	Initial commit of SRDL2SV	2021-05-02 00:58:43 +02:00

Dennis b7c1a12179

Add support for enumeration encoding

Fields that are encoded as enumerations are now recognized by the
application. All relevant information will be saved in the Field Object
and the variables and I/O list will be generated accordingly.

This commit also adds dynamic padding of the I/O and variable lists.

Still lacking is the automatic generation of SV packages.

2021-05-24 11:41:45 +02:00

srdl2sv

Add support for enumeration encoding

2021-05-24 11:41:45 +02:00

.gitignore

Initial commit of SRDL2SV

2021-05-02 00:58:43 +02:00

LIMITATIONS.md

Initial commit of SRDL2SV

2021-05-02 00:58:43 +02:00