A SystemRDL 2.0 to (synthesizable) SystemVerilog compiler.

asicfpgahardware-description-languagehdlrdlregister-description-languageregisterssystemrdlsystemrdl-compilersystemverilogverilog

Dennis cecb73f07a Fundamental changes to the architecture of component classes ... All components (e.g., fields, registers, addrmaps) are now children of a common class Component. This common class has certain common methods such as get_ports(), get_rtl(), or create_logger(). The AddrMap is now prepared to support alias registers by saving the registers in a dictionary. That way, registers can easily be accessed once an alias to a register is found. Furthermore, the addrmap template is now also loaded from a YAML file. Lastly, the first preparements to insert ports into the addrmap module are made. For templates, the indents do not need to be added anymore to the template. Now, a seperate method will automatically indent the RTL based on simple rules (e.g., increment indent if `begin` is found). The CLI also supports settings for the tabs (i.e., real tabs or spaces and the tab width). A lot of functionality from the __init__() method of the field class got reorganized. More logic will be reorganized in the future.		2021-05-15 00:29:59 +02:00
srdl2sv	Fundamental changes to the architecture of component classes	2021-05-15 00:29:59 +02:00
.gitignore	Initial commit of SRDL2SV	2021-05-02 00:58:43 +02:00
LIMITATIONS.md	Initial commit of SRDL2SV	2021-05-02 00:58:43 +02:00