mirror of
https://github.com/Silicon1602/srdl2sv.git
synced 2025-04-19 13:02:57 +00:00
Dennis
cecb73f07a
All components (e.g., fields, registers, addrmaps) are now children of a common class Component. This common class has certain common methods such as get_ports(), get_rtl(), or create_logger(). The AddrMap is now prepared to support alias registers by saving the registers in a dictionary. That way, registers can easily be accessed once an alias to a register is found. Furthermore, the addrmap template is now also loaded from a YAML file. Lastly, the first preparements to insert ports into the addrmap module are made. For templates, the indents do not need to be added anymore to the template. Now, a seperate method will automatically indent the RTL based on simple rules (e.g., increment indent if `begin` is found). The CLI also supports settings for the tabs (i.e., real tabs or spaces and the tab width). A lot of functionality from the __init__() method of the field class got reorganized. More logic will be reorganized in the future.
50 lines
1.3 KiB
YAML
50 lines
1.3 KiB
YAML
---
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sense_list_rst: |-
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always_ff @(posedge {clk_name} or {rst_edge} {rst_name})
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sense_list_no_rst: |-
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always_ff @(posedge {clk_name})
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rst_field_assign: |-
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if ({rst_negl}{rst_name})
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begin
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{path}_q{genvars} <= {rst_value};
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end
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else
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sw_access_field: |-
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if ({path}_sw_wr{genvars})
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begin
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sw_access_byte: |-
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if (byte_enable[{i}])
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begin
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{path}_q{genvars}[{msb_field}-:{field_w}] <= sw_wr_bus[{msb_bus}-:{bus_w}];
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end
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hw_access_we_wel: |-
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if ({negl}{path}_hw_wr{genvars})
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hw_access_no_we_wel: |-
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if (1) // we or wel property not set
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hw_access_field: |-
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begin
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{path}_q{genvars} <= {path}_in{genvars};
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end
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end_field_ff: |-
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end // of {path}'s always_ff
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field_comment: |-
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//-----------------FIELD SUMMARY-----------------
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// name : {name} ({path_wo_field}[{msb}:{lsb}])
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// access : hw = {hw_access} {hw_precedence}
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// sw = {sw_access} {sw_precedence}
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// reset : {rst_active} / {rst_type}
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// flags : {misc_flags}
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//-----------------------------------------------
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combo_operation_comment: |-
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// Combinational logic for {path}
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assign_combo_operation: |-
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assign {path}_{op_name}{genvars} = {op_verilog}{path}_q{genvars}
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singlepulse: |-
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begin
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{path}{genvars} <= 0;
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end
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