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https://github.com/Silicon1602/srdl2sv.git
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41 lines
1.2 KiB
Plaintext
41 lines
1.2 KiB
Plaintext
addrmap hierarchical_regfiles {
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regfile {
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reg {
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field {sw=rw; hw=rw; we;} f1 [15:0];
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field {sw=rw; hw=rw; we;} f2 [31:16];
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} reg_a;
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reg {
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field {sw=rw; hw=rw; we;} f1 [15:0];
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field {sw=rw; hw=rw; we;} f2 [31:16];
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} reg_b;
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} regfile_1;
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regfile {
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// Remove we property and set hw=w.
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// Set sw=r for one of the properties to generate a simple wire
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// Set sw=r/hw=r for one of the properties to generate a constant
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reg {
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field {sw=r; hw=w;} f1 [7:0];
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field {sw=r; hw=r;} f2 [15:8] = 42; // It's the meaning of life
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field {sw=rw; hw=w;} f3 [31:16];
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} reg_c;
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// Another level of regfile-hierarchy
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regfile {
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// Remove we property, to show yet another type of register
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reg {
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field {sw=rw; hw=rw;} f1 [15:0];
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field {sw=rw; hw=rw;} f2 [31:16];
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} reg_d;
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} regfile_3 [4][2];
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} regfile_2 [3];
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// Just a plain old register
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reg {
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field {sw=rw; hw=rw; we;} f1 [15:0];
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field {sw=rw; hw=rw; we;} f2 [31:16];
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} reg_e;
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};
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