parent
a43cd2ea6c
commit
82b2490256
GPG Key ID:
186A8AD440942BAF
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@ -20,7 +20,7 @@
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*
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* Generation information:
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* - User: : dpotter
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* - Time : October 31 2021 13:59:16
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* - Time : October 31 2021 16:01:37
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* - Path : /home/dpotter/srdl2sv/examples/enums
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* - RDL file : ['enums.rdl']
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* - Hostname : ArchXPS
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@ -35,6 +35,7 @@
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* - Use Real Tabs : False
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* - Tab Width : 4
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* - Enums Enabled : True
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* - Unpacked I/Os : True
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* - Register Bus Type: amba3ahblite
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* - Address width : 32
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* - Byte enables : True
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@ -83,26 +84,26 @@ module enums
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input [32-1:0] HWDATA ,
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input HSEL ,
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input enums_pkg::third_enum regfile_1__reg_c__f1_in,
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input logic [1:0] regfile_1__reg_c__f2_in,
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input [1:0] regfile_1__reg_c__f2_in,
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input enums__regfile_1_pkg::fourth_enum regfile_1__reg_d__f1_in,
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input logic [1:0] regfile_1__reg_d__f2_in,
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input [1:0] regfile_1__reg_d__f2_in,
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input enums_pkg::first_enum reg_a__f1_in ,
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input logic [1:0] reg_a__f2_in ,
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input [1:0] reg_a__f2_in ,
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input enums_pkg::second_enum reg_b__f1_in ,
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input logic [1:0] reg_b__f2_in ,
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input [1:0] reg_b__f2_in ,
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// Outputs
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output HREADYOUT ,
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output HRESP ,
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output [32-1:0] HRDATA ,
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output enums_pkg::third_enum regfile_1__reg_c__f1_r,
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output logic [1:0] regfile_1__reg_c__f2_r,
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output [1:0] regfile_1__reg_c__f2_r,
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output enums__regfile_1_pkg::fourth_enum regfile_1__reg_d__f1_r,
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output logic [1:0] regfile_1__reg_d__f2_r,
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output [1:0] regfile_1__reg_d__f2_r,
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output enums_pkg::first_enum reg_a__f1_r ,
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output logic [1:0] reg_a__f2_r ,
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output [1:0] reg_a__f2_r ,
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output enums_pkg::second_enum reg_b__f1_r ,
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output logic [1:0] reg_b__f2_r
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output [1:0] reg_b__f2_r
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);
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@ -30,7 +30,7 @@ addrmap hierarchical_regfiles {
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field {sw=rw; hw=rw;} f2 [31:16];
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} reg_d;
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} regfile_3 [4][2];
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} regfile_2 [2];
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} regfile_2 [3];
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// Just a plain old register
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reg {
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@ -20,7 +20,7 @@
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*
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* Generation information:
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* - User: : dpotter
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* - Time : October 30 2021 23:34:40
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* - Time : October 31 2021 15:59:23
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* - Path : /home/dpotter/srdl2sv/examples/hierarchical_regfiles
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* - RDL file : ['hierarchical_regfiles.rdl']
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* - Hostname : ArchXPS
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@ -35,6 +35,7 @@
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* - Use Real Tabs : False
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* - Tab Width : 4
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* - Enums Enabled : True
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* - Unpacked I/Os : True
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* - Register Bus Type: amba3ahblite
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* - Address width : 32
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* - Byte enables : True
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@ -81,36 +82,36 @@ module hierarchical_regfiles
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input [1:0] HTRANS ,
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input [32-1:0] HWDATA ,
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input HSEL ,
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input logic regfile_1__reg_a__f1_hw_wr ,
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input logic [15:0] regfile_1__reg_a__f1_in ,
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input logic regfile_1__reg_a__f2_hw_wr ,
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input logic [15:0] regfile_1__reg_a__f2_in ,
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input logic regfile_1__reg_b__f1_hw_wr ,
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input logic [15:0] regfile_1__reg_b__f1_in ,
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input logic regfile_1__reg_b__f2_hw_wr ,
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input logic [15:0] regfile_1__reg_b__f2_in ,
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input logic [15:0] regfile_2__regfile_3__reg_d__f1_in[2][4][2],
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input logic [15:0] regfile_2__regfile_3__reg_d__f2_in[2][4][2],
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input logic [7:0] regfile_2__reg_c__f1_in [2],
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input logic [15:0] regfile_2__reg_c__f3_in [2],
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input logic reg_e__f1_hw_wr ,
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input logic [15:0] reg_e__f1_in ,
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input logic reg_e__f2_hw_wr ,
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input logic [15:0] reg_e__f2_in ,
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input regfile_1__reg_a__f1_hw_wr ,
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input [15:0] regfile_1__reg_a__f1_in ,
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input regfile_1__reg_a__f2_hw_wr ,
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input [15:0] regfile_1__reg_a__f2_in ,
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input regfile_1__reg_b__f1_hw_wr ,
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input [15:0] regfile_1__reg_b__f1_in ,
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input regfile_1__reg_b__f2_hw_wr ,
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input [15:0] regfile_1__reg_b__f2_in ,
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input [15:0] regfile_2__regfile_3__reg_d__f1_in[3][4][2],
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input [15:0] regfile_2__regfile_3__reg_d__f2_in[3][4][2],
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input [7:0] regfile_2__reg_c__f1_in [3],
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input [15:0] regfile_2__reg_c__f3_in [3],
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input reg_e__f1_hw_wr ,
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input [15:0] reg_e__f1_in ,
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input reg_e__f2_hw_wr ,
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input [15:0] reg_e__f2_in ,
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// Outputs
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output HREADYOUT ,
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output HRESP ,
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output [32-1:0] HRDATA ,
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output logic [15:0] regfile_1__reg_a__f1_r ,
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output logic [15:0] regfile_1__reg_a__f2_r ,
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output logic [15:0] regfile_1__reg_b__f1_r ,
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output logic [15:0] regfile_1__reg_b__f2_r ,
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output logic [15:0] regfile_2__regfile_3__reg_d__f1_r[2][4][2],
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output logic [15:0] regfile_2__regfile_3__reg_d__f2_r[2][4][2],
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output logic [7:0] regfile_2__reg_c__f2_r [2],
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output logic [15:0] reg_e__f1_r ,
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output logic [15:0] reg_e__f2_r
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output [15:0] regfile_1__reg_a__f1_r ,
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output [15:0] regfile_1__reg_a__f2_r ,
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output [15:0] regfile_1__reg_b__f1_r ,
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output [15:0] regfile_1__reg_b__f2_r ,
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output [15:0] regfile_2__regfile_3__reg_d__f1_r[3][4][2],
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output [15:0] regfile_2__regfile_3__reg_d__f2_r[3][4][2],
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output [7:0] regfile_2__reg_c__f2_r [3],
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output [15:0] reg_e__f1_r ,
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output [15:0] reg_e__f2_r
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);
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@ -352,32 +353,32 @@ assign regfile_1__reg_b_err_mux_in = !((widget_if.r_vld && (widget_if.byte_en[0]
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*******************************************************************
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* REGFILE : regfile_2
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* DIMENSION : 1
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* DEPTHS (per dimension): [2]
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* DEPTHS (per dimension): [3]
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*******************************************************************
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*******************************************************************/
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// Variables of register 'reg_d'
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logic regfile_2__regfile_3__reg_d_active [2][4][2];
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logic regfile_2__regfile_3__reg_d_sw_wr [2][4][2];
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logic [31:0] regfile_2__regfile_3__reg_d_data_mux_in[2][4][2];
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logic regfile_2__regfile_3__reg_d_rdy_mux_in [2][4][2];
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logic regfile_2__regfile_3__reg_d_err_mux_in [2][4][2];
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logic [15:0] regfile_2__regfile_3__reg_d__f1_q [2][4][2];
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logic [15:0] regfile_2__regfile_3__reg_d__f2_q [2][4][2];
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logic regfile_2__regfile_3__reg_d_active [3][4][2];
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logic regfile_2__regfile_3__reg_d_sw_wr [3][4][2];
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logic [31:0] regfile_2__regfile_3__reg_d_data_mux_in[3][4][2];
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logic regfile_2__regfile_3__reg_d_rdy_mux_in [3][4][2];
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logic regfile_2__regfile_3__reg_d_err_mux_in [3][4][2];
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logic [15:0] regfile_2__regfile_3__reg_d__f1_q [3][4][2];
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logic [15:0] regfile_2__regfile_3__reg_d__f2_q [3][4][2];
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// Variables of register 'reg_c'
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logic regfile_2__reg_c_active [2];
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logic regfile_2__reg_c_sw_wr [2];
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logic [31:0] regfile_2__reg_c_data_mux_in[2];
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logic regfile_2__reg_c_rdy_mux_in [2];
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logic regfile_2__reg_c_err_mux_in [2];
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logic [7:0] regfile_2__reg_c__f1_q [2];
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logic [7:0] regfile_2__reg_c__f2_q [2];
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logic [15:0] regfile_2__reg_c__f3_q [2];
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logic regfile_2__reg_c_active [3];
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logic regfile_2__reg_c_sw_wr [3];
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logic [31:0] regfile_2__reg_c_data_mux_in[3];
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logic regfile_2__reg_c_rdy_mux_in [3];
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logic regfile_2__reg_c_err_mux_in [3];
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logic [7:0] regfile_2__reg_c__f1_q [3];
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logic [7:0] regfile_2__reg_c__f2_q [3];
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logic [15:0] regfile_2__reg_c__f3_q [3];
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generate
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for (gv_a = 0; gv_a < 2; gv_a++)
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for (gv_a = 0; gv_a < 3; gv_a++)
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begin
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/*******************************************************************
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*******************************************************************
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@ -586,7 +587,7 @@ logic [15:0] reg_e__f2_q ;
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// Register-activation for 'reg_e'
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assign reg_e_active = widget_if.addr == 136;
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assign reg_e_active = widget_if.addr == 172;
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assign reg_e_sw_wr = reg_e_active && widget_if.w_vld;
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//-----------------FIELD SUMMARY-----------------
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@ -774,6 +775,54 @@ begin
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widget_if.err = regfile_2__regfile_3__reg_d_err_mux_in[1][3][1];
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widget_if.rdy = regfile_2__regfile_3__reg_d_rdy_mux_in[1][3][1];
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end
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regfile_2__regfile_3__reg_d_active[2][0][0]:
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begin
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widget_if.r_data = regfile_2__regfile_3__reg_d_data_mux_in[2][0][0];
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widget_if.err = regfile_2__regfile_3__reg_d_err_mux_in[2][0][0];
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widget_if.rdy = regfile_2__regfile_3__reg_d_rdy_mux_in[2][0][0];
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end
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regfile_2__regfile_3__reg_d_active[2][0][1]:
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begin
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widget_if.r_data = regfile_2__regfile_3__reg_d_data_mux_in[2][0][1];
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widget_if.err = regfile_2__regfile_3__reg_d_err_mux_in[2][0][1];
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widget_if.rdy = regfile_2__regfile_3__reg_d_rdy_mux_in[2][0][1];
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end
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regfile_2__regfile_3__reg_d_active[2][1][0]:
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begin
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widget_if.r_data = regfile_2__regfile_3__reg_d_data_mux_in[2][1][0];
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widget_if.err = regfile_2__regfile_3__reg_d_err_mux_in[2][1][0];
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widget_if.rdy = regfile_2__regfile_3__reg_d_rdy_mux_in[2][1][0];
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end
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regfile_2__regfile_3__reg_d_active[2][1][1]:
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begin
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widget_if.r_data = regfile_2__regfile_3__reg_d_data_mux_in[2][1][1];
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widget_if.err = regfile_2__regfile_3__reg_d_err_mux_in[2][1][1];
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widget_if.rdy = regfile_2__regfile_3__reg_d_rdy_mux_in[2][1][1];
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end
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regfile_2__regfile_3__reg_d_active[2][2][0]:
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begin
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widget_if.r_data = regfile_2__regfile_3__reg_d_data_mux_in[2][2][0];
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widget_if.err = regfile_2__regfile_3__reg_d_err_mux_in[2][2][0];
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widget_if.rdy = regfile_2__regfile_3__reg_d_rdy_mux_in[2][2][0];
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end
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regfile_2__regfile_3__reg_d_active[2][2][1]:
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begin
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widget_if.r_data = regfile_2__regfile_3__reg_d_data_mux_in[2][2][1];
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widget_if.err = regfile_2__regfile_3__reg_d_err_mux_in[2][2][1];
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widget_if.rdy = regfile_2__regfile_3__reg_d_rdy_mux_in[2][2][1];
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end
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regfile_2__regfile_3__reg_d_active[2][3][0]:
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begin
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widget_if.r_data = regfile_2__regfile_3__reg_d_data_mux_in[2][3][0];
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widget_if.err = regfile_2__regfile_3__reg_d_err_mux_in[2][3][0];
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widget_if.rdy = regfile_2__regfile_3__reg_d_rdy_mux_in[2][3][0];
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end
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regfile_2__regfile_3__reg_d_active[2][3][1]:
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begin
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widget_if.r_data = regfile_2__regfile_3__reg_d_data_mux_in[2][3][1];
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widget_if.err = regfile_2__regfile_3__reg_d_err_mux_in[2][3][1];
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widget_if.rdy = regfile_2__regfile_3__reg_d_rdy_mux_in[2][3][1];
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end
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regfile_2__reg_c_active[0]:
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begin
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widget_if.r_data = regfile_2__reg_c_data_mux_in[0];
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@ -786,6 +835,12 @@ begin
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widget_if.err = regfile_2__reg_c_err_mux_in[1];
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widget_if.rdy = regfile_2__reg_c_rdy_mux_in[1];
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end
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regfile_2__reg_c_active[2]:
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begin
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widget_if.r_data = regfile_2__reg_c_data_mux_in[2];
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widget_if.err = regfile_2__reg_c_err_mux_in[2];
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widget_if.rdy = regfile_2__reg_c_rdy_mux_in[2];
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end
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reg_e_active:
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begin
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widget_if.r_data = reg_e_data_mux_in;
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@ -20,7 +20,7 @@
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*
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* Generation information:
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* - User: : dpotter
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* - Time : October 30 2021 23:34:49
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* - Time : October 31 2021 15:59:28
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* - Path : /home/dpotter/srdl2sv/examples/interrupt_hierarchy
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* - RDL file : ['interrupt_hierarchy.rdl']
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* - Hostname : ArchXPS
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@ -35,6 +35,7 @@
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* - Use Real Tabs : False
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* - Tab Width : 4
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* - Enums Enabled : True
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* - Unpacked I/Os : True
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* - Register Bus Type: amba3ahblite
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* - Address width : 32
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* - Byte enables : True
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@ -81,40 +82,40 @@ module interrupt_hierarchy
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input [1:0] HTRANS ,
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input [32-1:0] HWDATA ,
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input HSEL ,
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input logic [0:0] block_a_int__crc_error_in ,
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input logic [0:0] block_a_int__len_error_in ,
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input logic [0:0] block_a_int__multi_bit_ecc_error_in,
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input logic [3:0] block_a_int__active_ecc_master_in ,
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input logic [0:0] block_b_int__crc_error_in ,
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input logic [0:0] block_b_int__len_error_in ,
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input logic [0:0] block_b_int__multi_bit_ecc_error_in,
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input logic [3:0] block_b_int__active_ecc_master_in ,
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input logic [0:0] block_c_int__crc_error_in ,
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input logic [0:0] block_c_int__len_error_in ,
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input logic [0:0] block_c_int__multi_bit_ecc_error_in,
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input logic [3:0] block_c_int__active_ecc_master_in ,
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input logic [0:0] block_d_int__crc_error_in ,
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input logic [0:0] block_d_int__len_error_in ,
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input logic [0:0] block_d_int__multi_bit_ecc_error_in,
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input logic [3:0] block_d_int__active_ecc_master_in ,
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input [0:0] block_a_int__crc_error_in ,
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input [0:0] block_a_int__len_error_in ,
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input [0:0] block_a_int__multi_bit_ecc_error_in,
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input [3:0] block_a_int__active_ecc_master_in ,
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input [0:0] block_b_int__crc_error_in ,
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input [0:0] block_b_int__len_error_in ,
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input [0:0] block_b_int__multi_bit_ecc_error_in,
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input [3:0] block_b_int__active_ecc_master_in ,
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input [0:0] block_c_int__crc_error_in ,
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input [0:0] block_c_int__len_error_in ,
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input [0:0] block_c_int__multi_bit_ecc_error_in,
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input [3:0] block_c_int__active_ecc_master_in ,
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input [0:0] block_d_int__crc_error_in ,
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input [0:0] block_d_int__len_error_in ,
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input [0:0] block_d_int__multi_bit_ecc_error_in,
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input [3:0] block_d_int__active_ecc_master_in ,
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// Outputs
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output HREADYOUT ,
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output HRESP ,
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output [32-1:0] HRDATA ,
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output logic block_a_int_intr,
|
||||
output logic block_a_int_halt,
|
||||
output logic block_b_int_intr,
|
||||
output logic block_b_int_halt,
|
||||
output logic block_c_int_intr,
|
||||
output logic block_c_int_halt,
|
||||
output logic block_d_int_intr,
|
||||
output logic block_d_int_halt,
|
||||
output logic master_int_intr ,
|
||||
output logic master_halt_intr,
|
||||
output logic master_halt_halt,
|
||||
output logic global_int_intr ,
|
||||
output logic global_int_halt
|
||||
output block_a_int_intr,
|
||||
output block_a_int_halt,
|
||||
output block_b_int_intr,
|
||||
output block_b_int_halt,
|
||||
output block_c_int_intr,
|
||||
output block_c_int_halt,
|
||||
output block_d_int_intr,
|
||||
output block_d_int_halt,
|
||||
output master_int_intr ,
|
||||
output master_halt_intr,
|
||||
output master_halt_halt,
|
||||
output global_int_intr ,
|
||||
output global_int_halt
|
||||
);
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -20,7 +20,7 @@
|
|||
*
|
||||
* Generation information:
|
||||
* - User: : dpotter
|
||||
* - Time : October 30 2021 23:34:53
|
||||
* - Time : October 31 2021 15:59:35
|
||||
* - Path : /home/dpotter/srdl2sv/examples/simple_rw_reg
|
||||
* - RDL file : ['simple_rw_reg.rdl']
|
||||
* - Hostname : ArchXPS
|
||||
|
|
@ -35,6 +35,7 @@
|
|||
* - Use Real Tabs : False
|
||||
* - Tab Width : 4
|
||||
* - Enums Enabled : True
|
||||
* - Unpacked I/Os : True
|
||||
* - Register Bus Type: amba3ahblite
|
||||
* - Address width : 32
|
||||
* - Byte enables : True
|
||||
|
|
@ -81,29 +82,29 @@ module simple_rw_reg
|
|||
input [1:0] HTRANS ,
|
||||
input [32-1:0] HWDATA ,
|
||||
input HSEL ,
|
||||
input logic register_1d__f1_hw_wr,
|
||||
input logic [15:0] register_1d__f1_in ,
|
||||
input logic register_1d__f2_hw_wr,
|
||||
input logic [15:0] register_1d__f2_in ,
|
||||
input logic register_2d__f1_hw_wr[2],
|
||||
input logic [15:0] register_2d__f1_in [2],
|
||||
input logic register_2d__f2_hw_wr[2],
|
||||
input logic [15:0] register_2d__f2_in [2],
|
||||
input logic register_3d__f1_hw_wr[2][2],
|
||||
input logic [15:0] register_3d__f1_in [2][2],
|
||||
input logic register_3d__f2_hw_wr[2][2],
|
||||
input logic [15:0] register_3d__f2_in [2][2],
|
||||
input register_1d__f1_hw_wr,
|
||||
input [15:0] register_1d__f1_in ,
|
||||
input register_1d__f2_hw_wr,
|
||||
input [15:0] register_1d__f2_in ,
|
||||
input register_2d__f1_hw_wr[2],
|
||||
input [15:0] register_2d__f1_in [2],
|
||||
input register_2d__f2_hw_wr[2],
|
||||
input [15:0] register_2d__f2_in [2],
|
||||
input register_3d__f1_hw_wr[2][2],
|
||||
input [15:0] register_3d__f1_in [2][2],
|
||||
input register_3d__f2_hw_wr[2][2],
|
||||
input [15:0] register_3d__f2_in [2][2],
|
||||
|
||||
// Outputs
|
||||
output HREADYOUT ,
|
||||
output HRESP ,
|
||||
output [32-1:0] HRDATA ,
|
||||
output logic [15:0] register_1d__f1_r,
|
||||
output logic [15:0] register_1d__f2_r,
|
||||
output logic [15:0] register_2d__f1_r[2],
|
||||
output logic [15:0] register_2d__f2_r[2],
|
||||
output logic [15:0] register_3d__f1_r[2][2],
|
||||
output logic [15:0] register_3d__f2_r[2][2]
|
||||
output [15:0] register_1d__f1_r,
|
||||
output [15:0] register_1d__f2_r,
|
||||
output [15:0] register_2d__f1_r[2],
|
||||
output [15:0] register_2d__f2_r[2],
|
||||
output [15:0] register_3d__f1_r[2][2],
|
||||
output [15:0] register_3d__f2_r[2][2]
|
||||
);
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue