Dennis d3bfdeb3f0 Buswidth is now variable, based on widest register ... Fixes #2.		2021-09-26 21:16:49 -07:00
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external_registers.rdl	Add directory that will contain SystemRDL files for tests	2021-09-13 22:09:04 -07:00
interrupts.rdl	Finish initial version of interrupt suport, closes #1	2021-09-26 19:40:04 -07:00
simple_rw_reg.rdl	Buswidth is now variable, based on widest register	2021-09-26 21:16:49 -07:00