mirror of
https://github.com/Silicon1602/srdl2sv.git
synced 2024-12-22 15:08:39 +00:00
Dennis
6deb772196
The software itself is licensed under the copy-left GPL-3.0 license. All RTL (i.e., templates and widgets) are licensed under the MIT license. Therefore, the generated RTL will not be subject to the GPL-3.0 but to the MIT license.
83 lines
4.8 KiB
Markdown
83 lines
4.8 KiB
Markdown
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# Introduction
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srdl2sv is a [SystemRDL 2.0](https://www.accellera.org/images/downloads/standards/systemrdl/SystemRDL_2.0_Jan2018.pdf) to (synthesizable) [SystemVerilog](https://ieeexplore.ieee.org/document/8299595/versions) compiler. The tool is based on based on [SystemRDL/systemrdl-compiler](https://github.com/SystemRDL/systemrdl-compiler).
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## ⚠️ Non-production ready
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Warning! This software is still under development and not yet ready for use in production.
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# Getting started
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## Installation
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## Compiling your first RDL
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The argument that is required to get started is the location of the SystemRDL file that contains the root address map. The compiler will generate a seperate SystemVerilog module for each address map it encounters in the code. Thus, if address maps are instantiated within other address maps, these will be packed into a seperate module.
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To compile a file called `example_addrmap.rdl`, simply run:
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```
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srdl2sv example_addrmap.rdl
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```
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By default, the compiler will create a directory called `srdl2sv_out` and dump `example_addrmap.sv` with the actual RTL and a log file that contains `INFO`-level logging into this directory. To change the logging level, use `--file_log_level` like shown below:
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```
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srdl2sv example_addrmap.rdl
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--stream_log_level {DEBUG,INFO,WARNING,ERROR,CRITICAL,NONE}
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```
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Similarly, to change the default log level of the output to the shell, which is `WARNING`, use `--stream_log_level` like shown below:
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```
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srdl2sv example_addrmap.rdl
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--stream_log_level {DEBUG,INFO,WARNING,ERROR,CRITICAL,NONE}
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--file_log_level {DEBUG,INFO,WARNING,ERROR,CRITICAL,NONE}
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```
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If the RDL file includes other RDL files, the directories that contain these files must be passed to the compiler as follows:
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```
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srdl2sv example_addrmap.rdl
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--search_paths SEARCH_PATHS [SEARCH_PATHS ...]
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```
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## Using the generated RTL
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## Help function
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A comprehensive help function of the tool can be invoked by running `srdl2sv --help`.
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```
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usage: main.py [-h] [-b {amba3ahblite}] [-o OUT_DIR] [-d SEARCH_PATHS [SEARCH_PATHS ...]] [-r] [-x]
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[-e] [--stream_log_level {DEBUG,INFO,WARNING,ERROR,CRITICAL,NONE}]
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[--file_log_level {DEBUG,INFO,WARNING,ERROR,CRITICAL,NONE}] [--real_tabs]
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[--tab_width TAB_WIDTH]
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IN_RDL [IN_RDL ...]
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SystemRDL 2 SystemVerilog compiler
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positional arguments:
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IN_RDL Location of RDL file(s) with root addrmap.
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optional arguments:
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-h, --help show this help message and exit
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-b {amba3ahblite}, --bus {amba3ahblite}
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Set the bus protocol that shall be used by software to ', communicate with the
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registers. (default: amba3ahblite)
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-o OUT_DIR, --out_dir OUT_DIR
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Define output directory to dump files. If directory is non-existent, it will
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be created. (default: ./srdl2sv_out)
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-d SEARCH_PATHS [SEARCH_PATHS ...], --search_paths SEARCH_PATHS [SEARCH_PATHS ...]
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Point to one (or more) directories that will be searched for RDL files.
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-r, --recursive_search
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If set, the dependency directories will be searched recursively.
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-x, --disable_sanity Disable sanity checks or components. This might speed up the compiler but is
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generally not recommended!
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-e, --disable_enums Disable enumeration generation. This will prevent the compiler from generating
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packages and it will prevent it from using enums in the port list.
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--stream_log_level {DEBUG,INFO,WARNING,ERROR,CRITICAL,NONE}
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Set verbosity level of output to shell. When set to 'NONE', nothing will be
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printed to the shell. (default: WARNING)
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--file_log_level {DEBUG,INFO,WARNING,ERROR,CRITICAL,NONE}
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Set verbosity level of output to log-file. When set to 'NONE', nothing will be
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printed to the shell. (default: INFO)
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--real_tabs Use tabs, rather than spaces, for tabs
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--tab_width TAB_WIDTH
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Define how many tabs or spaces will be contained in one level of indentation.
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(default: 4)
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```
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# Contributing
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# License
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The source code of srdl2sv (i.e., the actual RTL generator) is licensed under the [GPLv3](LICENSE). All templates in [srdlsv/components/templates](srdlsv/components/templates) and [srdlsv/components/widgets](srdlsv/components/widgets) are licensed under the [MIT](LICENSE.MIT) license. Therefore, all RTL that is generated by srdl2sv is also licensed under the MIT license.
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# Limitations
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- [Any limitations to the systemrdl-compiler](https://systemrdl-compiler.readthedocs.io/en/latest/known_issues.html) also apply to the SystemRDL2SystemVerilog compiler.
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- Depth of a hierarchy is limited to 26 levels.
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