Dennis Potter Dennis

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• Joined on 2018-03-10

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srdl2sv

Python 0 0

A SystemRDL 2.0 to (synthesizable) SystemVerilog compiler.

asic systemverilog systemrdl-compiler systemrdl registers register-description-language rdl hdl hardware-description-language fpga verilog

Updated 2021-11-27 00:53:06 +00:00