srdl2sv is a [SystemRDL 2.0](https://www.accellera.org/images/downloads/standards/systemrdl/SystemRDL_2.0_Jan2018.pdf) to (synthesizable) [SystemVerilog](https://ieeexplore.ieee.org/document/8299595/versions) compiler. The tool is based on based on [SystemRDL/systemrdl-compiler](https://github.com/SystemRDL/systemrdl-compiler).
This tool does not generate any documentation, UVM files, or IP_XACT XML. To create those files, one can use [PeakRDL-html](https://github.com/SystemRDL/PeakRDL-html), [PeakRDL-uvm](https://github.com/SystemRDL/PeakRDL-uvm), or [PeakRDL-ipxact](https://github.com/SystemRDL/PeakRDL-ipxact), respectively. Since All these tools are based on the systemrdl-compiler that is also at the base of srdl2sv it is possible to generate a wrapper that uses the same instance tree for all 4 tools.
Warning: This software is still under development and not yet ready for use in production. Many SystemRDL features are implemented but srdl2sv is still under active development and almost all tests are yet to be written.
A `setup.py` file is provided to install srdl2sv and all dependencies. At the time of writing this, the software has only been tested on Linux but there should not be anything that prevents it from running on MacOS, Windows, or any other OS with Python >= 3.8.
The argument that is required to get started is the location of the SystemRDL file that contains the root address map. The compiler will generate a seperate SystemVerilog module for each address map it encounters in the code. Thus, if address maps are instantiated within other address maps, these will be packed into a seperate module.
To compile a file called `example_addrmap.rdl`, simply run:
By default, the compiler will create a directory called `srdl2sv_out` and dump `example_addrmap.sv` with the actual RTL. By default, the program wil not dump any logging into this directory. To change the logging level, use `--file-logging` like shown below:
By default, the compiler will generate SystemVerilog enumerations if SystemRDL enums are used. These enums are dumped in a seperate package to be included outside of the register module. To turn off this feature, use the flag `--no-enums`:
By default, the registers in the RTL are byte-addressable. If this is not required it is recommened to turn off byte-addressing by using the flag `--no-byte-enable` to achieve more efficient results in synthesis:
For the generated RTL to work, all files in `srdl2sv_out` (or in a custom directory, if specified with `-o` must be passed on to the respective EDA tool for proper functioning. For a better understanding of the files that get generated, a short summary below.
A run with only 1 `addrmap`, without any enumerations, and with `--bus simple` will generate 2 files:
```
srdl2sv_out/
├─ <addrmap_name>.sv
├─ srdl2sv_widget_if.sv
```
The former file is the actual SystemVerilog module that contains all register logic. The latter contains a SystemVerilog `interface` that is internally being used to enable communication with the registers. It is worth noting that the `interface` is **not** brought up to the module's interface but is flattened out for compatibility reasons.
If one decides to al create a bus protocol (see [Supported bus protocols](#supported-bus-protocols)), an additional file will be created that contains a SHIM between the protocol and the internal bus logic.
```
srdl2sv_out/
├─ <addrmap_name>.sv
├─ srdl2sv_widget_if.sv
├─ srdl2sv_<protocol_name>.sv
```
If an `addrmap` calls other `addrmaps`, each will get it's own SystemVerilog module. For example, if `<addrmap_name>` from the previous example would instantiate `<addrmap1_name>` and `<addrmap2_name>`, the following files would be generated:
In case we only 1 `addrmap` is compiled, that address map contains enumerations, and `--no-enums` is *not* set, a seperate package will be generated that defines those enums. These enumerations are used in the module's I/O interface but can also be easily used outside of the `<addrmap_name>.sv`. That way, the code outside of the register block becomes more readable and a user gets all benefits of SystemVerilog's strong type checking.
If the address map from the aforementioned example contains `regfiles`, these will open a seperate scope to prevent naming collisions. For example's sake, let's assume it instantiates the `regfiles``<regfile_1>` and `<regfile_2>`. In that case, the following files would be dumped:
The source code of srdl2sv (i.e., the actual RTL generator) is licensed under the [GPLv3](LICENSE). All templates in [srdlsv/components/templates](https://github.com/Silicon1602/srdl2sv/tree/develop/srdl2sv/components/templates) and [srdlsv/components/widgets](https://github.com/Silicon1602/srdl2sv/tree/develop/srdl2sv/components/templates) are licensed under the MIT license. Therefore, all RTL that is generated by srdl2sv is also licensed under the MIT license.
- [Any limitations to the systemrdl-compiler](https://systemrdl-compiler.readthedocs.io/en/latest/known_issues.html) also apply to the SystemRDL2SystemVerilog compiler.
