srdl2sv/tests/systemrdl/simple_rw_reg.rdl

addrmap simple_rw_reg {
    reg {
        regwidth = 64;
        field {sw=rw; hw=rw;} f1 [15:0];
        field {sw=rw; hw=rw;} f2 [31:16];
    } register_0 [2];
};