mirror of
https://github.com/Silicon1602/srdl2sv.git
synced 2024-11-14 03:03:35 +00:00
Provide more advanced way of adding internal signals or ports
Now, every snippet of RTL in the YAML file can also hold internal variables (i.e., signals), input or output ports. Furthermore, the input/output port lists are replaced by a dictionary to prevent duplicate entries.
This commit is contained in:
parent
c5755bf104
commit
085e2ea2dc
GPG Key ID:
186A8AD440942BAF
@ -33,6 +33,7 @@ class AddrMap(Component):
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# We need a dictionary since it might be required to access the objects later
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# by name (for example, in case of aliases)
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self.registers = dict()
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self.rdl_nodes = dict()
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# Traverse through children
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for child in obj.children():
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@ -61,24 +62,26 @@ class AddrMap(Component):
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# Input ports
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input_ports_rtl = [
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AddrMap.templ_dict['input_port'].format(
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name = x.name,
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packed_dim = x.packed_dim,
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name = key,
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signal_type = value[0],
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unpacked_dim = '[{}]'.format(
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']['.join(
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[str(y) for y in x.unpacked_dim]))
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if x.unpacked_dim else '')
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for x in self.get_ports('input')]
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[str(y) for y in value[1]]))
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if value[1] else '')
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for (key, value) in self.get_ports('input').items()
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]
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# Output ports
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output_ports_rtl = [
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AddrMap.templ_dict['output_port'].format(
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name = x.name,
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packed_dim = x.packed_dim,
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name = key,
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signal_type = value[0],
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unpacked_dim = '[{}]'.format(
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']['.join(
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[str(y) for y in x.unpacked_dim]))
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if x.unpacked_dim else '')
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for x in self.get_ports('output')]
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[str(y) for y in value[1]]))
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if value[1] else '')
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for (key, value) in self.get_ports('output').items()
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]
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# Remove comma from last port entry
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output_ports_rtl[-1] = output_ports_rtl[-1].rstrip(',')
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@ -7,10 +7,13 @@ from systemrdl import node
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from log.log import create_logger
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# Define NamedTuple
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class Port(NamedTuple):
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class TypeDefMembers(NamedTuple):
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name: str
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packed_dim: str
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unpacked_dim: list
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member_type: str
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class TypeDef(NamedTuple):
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name: str
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members: list[TypeDefMembers]
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class Component():
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def __init__(self):
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@ -18,9 +21,10 @@ class Component():
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self.rtl_footer = []
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self.children = []
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self.ports = dict()
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self.ports['input'] = []
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self.ports['output'] = []
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self.ports['inout'] = []
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self.signals = dict()
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self.ports['input'] = dict()
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self.ports['output'] = dict()
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self.field_type = ''
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def create_logger(self, name: str, config: dict):
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self.logger = create_logger(
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@ -32,10 +36,19 @@ class Component():
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def get_ports(self, port_type: str):
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self.logger.debug("Return port list")
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return [
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*self.ports[port_type],
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*list(chain(*[x.get_ports(port_type) for x in self.children]))
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]
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for x in self.children:
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self.ports[port_type] |= x.get_ports(port_type)
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return self.ports[port_type]
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def get_signals(self):
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self.logger.debug("Return signal list")
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for x in self.children:
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self.signals |= x.get_signals()
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return self.signals
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def get_rtl(self, tab_width: int = 0, real_tabs: bool = False) -> str:
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self.logger.debug("Return RTL")
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@ -102,25 +115,60 @@ class Component():
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@staticmethod
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def split_dimensions(path: str):
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new_path = re.match(r'(.*?)(\[.*\])?(.*)', path)
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return (''.join([new_path.group(1), new_path.group(3)]),
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new_path.group(2) if new_path.group(2) else '[0]')
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re_dimensions = re.compile('(\[[^]]\])')
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new_path = re_dimensions.sub('', path)
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return (new_path, ''.join(re_dimensions.findall(path)))
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@staticmethod
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def get_ref_name(obj):
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def get_signal_name(obj):
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name = []
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try:
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child_obj = obj.node
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except AttributeError:
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child_obj = obj
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split_name = Component.split_dimensions(
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Component.get_underscored_path(
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obj.get_path(),
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obj.owning_addrmap.inst_name)
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child_obj.get_path(),
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child_obj.owning_addrmap.inst_name)
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)
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name.append(split_name[0])
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if isinstance(obj, (node.FieldNode)):
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if isinstance(obj, node.FieldNode):
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name.append('_q')
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elif isinstance(obj, node.SignalNode):
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pass
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else:
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name.append('_')
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name.append(obj.name)
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name.append(split_name[1])
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return ''.join(name)
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def yaml_signals_to_list(self, yaml_obj):
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try:
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for x in yaml_obj['signals']:
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self.signals[x['name'].format(path = self.path_underscored)] =\
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(x['signal_type'].format(field_type = self.field_type),
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self.array_dimensions)
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except (TypeError, KeyError):
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pass
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try:
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for x in yaml_obj['input_ports']:
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self.ports['input'][x['name'].format(path = self.path_underscored)] =\
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(x['signal_type'].format(field_type = self.field_type),
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self.array_dimensions)
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except (TypeError, KeyError):
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pass
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try:
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for x in yaml_obj['output_ports']:
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self.ports['output'][x['name'].format(path = self.path_underscored)] =\
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(x['signal_type'].format(field_type = self.field_type),
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self.array_dimensions)
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except (TypeError, KeyError):
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pass
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@ -7,7 +7,7 @@ from systemrdl.node import FieldNode
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from systemrdl.rdltypes import PrecedenceType, AccessType, OnReadType, OnWriteType
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# Local modules
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from components.component import Component, Port
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from components.component import Component
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from . import templates
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class Field(Component):
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@ -16,11 +16,11 @@ class Field(Component):
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pkg_resources.read_text(templates, 'fields.yaml'),
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Loader=yaml.FullLoader)
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def __init__(self, obj: node.FieldNode, dimensions: list, config:dict):
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def __init__(self, obj: node.FieldNode, array_dimensions: list, config:dict):
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super().__init__()
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# Save and/or process important variables
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self.__process_variables(obj, dimensions)
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self.__process_variables(obj, array_dimensions)
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# Create logger object
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self.create_logger("{}.{}".format(self.owning_addrmap, self.path), config)
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@ -40,49 +40,55 @@ class Field(Component):
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self.__add_access_rtl()
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self.__add_combo()
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self.__add_ports()
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self.__prepend_signal_declarations()
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def __add_combo(self):
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operations = []
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if self.obj.get_property('anded'):
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operations.append(['anded', '&'])
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operations.append(['&', 'assign_anded_operation'])
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if self.obj.get_property('ored'):
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operations.append(['ored', '|'])
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operations.append(['|', 'assign_ored_operation'])
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if self.obj.get_property('xored'):
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operations.append(['xored', '^'])
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operations.append(['^', 'assign_xored_operation'])
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if len(operations) > 0:
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self.rtl_header.append(
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Field.templ_dict['combo_operation_comment'].format(
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Field.templ_dict['combo_operation_comment']['rtl'].format(
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path = self.path_underscored))
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self.rtl_header = [
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*self.rtl_header,
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*[Field.templ_dict['assign_combo_operation'].format(
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*[Field.templ_dict[i[1]]['rtl'].format(
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path = self.path_underscored,
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genvars = self.genvars_str,
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op_name = i[0],
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op_verilog = i[1]) for i in operations]
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op_verilog = i[0]) for i in operations]
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]
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[self.yaml_signals_to_list(Field.templ_dict[i[1]]) for i in operations]
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def __process_variables(self, obj: node.RootNode, dimensions: list):
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def __process_variables(self, obj: node.RootNode, array_dimensions: list):
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# Save object
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self.obj = obj
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# Create full name
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self.owning_addrmap = obj.owning_addrmap.inst_name
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self.path = obj.get_path()\
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self.full_path = obj.get_path().replace('[]', '')
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self.path = self.full_path\
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.replace('[]', '')\
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.replace('{}.'.format(self.owning_addrmap), '')
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self.path_underscored = self.path.replace('.', '_')
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self.path_wo_field = '.'.join(self.path.split('.', -1)[0:-1])
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# Field type
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self.field_type = 'logic'
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# Save dimensions of unpacked dimension
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self.dimensions = dimensions
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self.array_dimensions = array_dimensions
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# Calculate how many genvars shall be added
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genvars = ['[{}]'.format(chr(97+i)) for i in range(len(dimensions))]
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genvars = ['[{}]'.format(chr(97+i)) for i in range(len(array_dimensions))]
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self.genvars_str = ''.join(genvars)
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# Write enable
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@ -138,7 +144,7 @@ class Field(Component):
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# Add comment with summary on field's properties
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return \
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Field.templ_dict['field_comment'].format(
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Field.templ_dict['field_comment']['rtl'].format(
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name = self.obj.inst_name,
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hw_access = str(self.hw_access)[11:],
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sw_access = str(self.sw_access)[11:],
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@ -156,7 +162,7 @@ class Field(Component):
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sense_list = 'sense_list_rst' if self.rst['async'] else 'sense_list_no_rst'
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self.rtl_header.append(
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Field.templ_dict[sense_list].format(
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Field.templ_dict[sense_list]['rtl'].format(
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clk_name = "clk",
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rst_edge = self.rst['edge'],
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rst_name = self.rst['name']))
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@ -164,15 +170,24 @@ class Field(Component):
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# Add actual reset line
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if self.rst['name']:
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self.rtl_header.append(
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Field.templ_dict['rst_field_assign'].format(
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Field.templ_dict['rst_field_assign']['rtl'].format(
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path = self.path_underscored,
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rst_name = self.rst['name'],
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rst_negl = "!" if self.rst['active'] == "active_high" else "",
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rst_value = self.rst['value'],
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genvars = self.genvars_str))
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self.yaml_signals_to_list(Field.templ_dict['rst_field_assign'])
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self.rtl_header.append("begin")
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# Add name of actual field to Signal field
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# TODO
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def __prepend_signal_declarations(self):
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pass
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def __add_access_rtl(self):
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# Not all access types are required and the order might differ
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# depending on what types are defined and what precedence is
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@ -191,19 +206,21 @@ class Field(Component):
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if self.hw_access in (AccessType.rw, AccessType.w):
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if self.we_or_wel:
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access_rtl['hw_write'].append(
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Field.templ_dict['hw_access_we_wel'].format(
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Field.templ_dict['hw_access_we_wel']['rtl'].format(
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negl = '!' if self.obj.get_property('wel') else '',
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path = self.path_underscored,
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genvars = self.genvars_str))
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else:
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access_rtl['hw_write'].append(
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Field.templ_dict['hw_access_no_we_wel'])
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Field.templ_dict['hw_access_no_we_wel']['rtl'])
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access_rtl['hw_write'].append(
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Field.templ_dict['hw_access_field'].format(
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Field.templ_dict['hw_access_field']['rtl'].format(
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path = self.path_underscored,
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genvars = self.genvars_str))
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self.yaml_signals_to_list(Field.templ_dict['hw_access_field'])
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# Define software access (if applicable)
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access_rtl['sw_write'] = []
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@ -213,19 +230,19 @@ class Field(Component):
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if isinstance(swwe, (node.FieldNode, node.SignalNode)):
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access_rtl['sw_write'].append(
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Field.templ_dict['sw_access_field_swwe'].format(
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Field.templ_dict['sw_access_field_swwe']['rtl'].format(
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path_wo_field = self.path_wo_field,
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genvars = self.genvars_str,
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swwe = Component.get_ref_name(swwe)))
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swwe = Component.get_signal_name(swwe)))
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elif isinstance(swwel, (node.FieldNode, node.SignalNode)):
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access_rtl['sw_write'].append(
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Field.templ_dict['sw_access_field_swwel'].format(
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Field.templ_dict['sw_access_field_swwel']['rtl'].format(
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path_wo_field = self.path_wo_field,
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genvars = self.genvars_str,
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swwel = Component.get_ref_name(swwel)))
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swwel = Component.get_signal_name(swwel)))
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else:
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access_rtl['sw_write'].append(
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Field.templ_dict['sw_access_field'].format(
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Field.templ_dict['sw_access_field']['rtl'].format(
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path_wo_field = self.path_wo_field,
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genvars = self.genvars_str))
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@ -237,7 +254,7 @@ class Field(Component):
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self.logger.warning("The OnReadType.wuser is not yet supported!")
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elif onwrite in (OnWriteType.wclr, OnWriteType.wset):
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access_rtl['sw_write'].append(
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Field.templ_dict[str(onwrite)].format(
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Field.templ_dict[str(onwrite)]['rtl'].format(
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path = self.path_underscored,
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genvars = self.genvars_str,
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path_wo_field = self.path_wo_field
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@ -247,7 +264,7 @@ class Field(Component):
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# If field spans multiple bytes, every byte shall have a seperate enable!
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for j, i in enumerate(range(self.lsbyte, self.msbyte+1)):
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access_rtl['sw_write'].append(
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Field.templ_dict[str(onwrite)].format(
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Field.templ_dict[str(onwrite)]['rtl'].format(
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path = self.path_underscored,
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genvars = self.genvars_str,
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i = i,
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@ -260,7 +277,7 @@ class Field(Component):
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# If field spans multiple bytes, every byte shall have a seperate enable!
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for j, i in enumerate(range(self.lsbyte, self.msbyte+1)):
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access_rtl['sw_write'].append(
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Field.templ_dict['sw_access_byte'].format(
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Field.templ_dict['sw_access_byte']['rtl'].format(
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path = self.path_underscored,
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genvars = self.genvars_str,
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i = i,
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@ -279,7 +296,7 @@ class Field(Component):
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self.logger.warning("The OnReadType.ruser is not yet supported!")
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else:
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access_rtl['sw_read'].append(
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Field.templ_dict[str(onread)].format(
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Field.templ_dict[str(onread)]['rtl'].format(
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path = self.path_underscored,
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genvars = self.genvars_str,
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path_wo_field = self.path_wo_field
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@ -289,7 +306,7 @@ class Field(Component):
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# Add singlepulse property
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if self.obj.get_property('singlepulse'):
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access_rtl['singlepulse'] = [
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Field.templ_dict['singlepulse'].format(
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Field.templ_dict['singlepulse']['rtl'].format(
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path = self.path_underscored,
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genvars = self.genvars_str)
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]
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@ -335,40 +352,19 @@ class Field(Component):
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self.rtl_header = [*self.rtl_header, *order_list_rtl]
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self.rtl_header.append(
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Field.templ_dict['end_field_ff'].format(
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Field.templ_dict['end_field_ff']['rtl'].format(
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path = self.path_underscored))
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def __add_ports(self):
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# Port is writable by hardware --> Input port from hardware
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if self.hw_access in (AccessType.rw, AccessType.w):
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self.ports['input'].append(
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Port("{}_in".format(self.path_underscored),
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"",
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self.dimensions
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))
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# Port has enable signal --> create such an enable
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if self.we_or_wel:
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self.ports['input'].append(
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Port("{}_hw_wr".format(self.path_underscored),
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"",
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self.dimensions
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))
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if self.hw_access in (AccessType.rw, AccessType.r):
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self.ports['output'].append(
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Port("{}_r".format(self.path_underscored),
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"[{}:0]".format(self.obj.width-1) if self.obj.width > 1 else "",
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self.dimensions
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))
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# Connect flops to output port
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self.rtl_header.append(
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Field.templ_dict['out_port_assign'].format(
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Field.templ_dict['out_port_assign']['rtl'].format(
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genvars = self.genvars_str,
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path = self.path_underscored))
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self.yaml_signals_to_list(Field.templ_dict['out_port_assign'])
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def sanity_checks(self):
|
||||
# If hw=rw/sw=[r]w and hw has no we/wel, sw will never be able to write
|
||||
@ -381,3 +377,6 @@ class Field(Component):
|
||||
"precedence for hardware will render software's "\
|
||||
"write property useless since hardware will "\
|
||||
"write every cycle.")
|
||||
|
||||
|
||||
# TODO: Counter & hw=r shouldn't work
|
||||
|
||||
@ -25,28 +25,6 @@ class Register(Component):
|
||||
self.create_logger("{}.{}".format(self.owning_addrmap, self.path), config)
|
||||
self.logger.debug('Starting to process register "{}"'.format(obj.inst_name))
|
||||
|
||||
# Create comment and provide user information about register he/she
|
||||
# is looking at.
|
||||
self.rtl_header.append(
|
||||
Register.templ_dict['reg_comment'].format(
|
||||
name = obj.inst_name,
|
||||
dimensions = self.dimensions,
|
||||
depth = self.depth))
|
||||
|
||||
# Create wires every register
|
||||
self.rtl_header.append(
|
||||
Register.templ_dict['rw_wire_declare'].format(
|
||||
path = self.path,
|
||||
depth = self.depth))
|
||||
|
||||
# Create generate block for register and add comment
|
||||
self.rtl_header.append("generate")
|
||||
for i in range(self.dimensions):
|
||||
self.rtl_header.append(
|
||||
Register.templ_dict['generate_for_start'].format(
|
||||
iterator = chr(97+i),
|
||||
limit = self.array_dimensions[i]))
|
||||
|
||||
# Create RTL for fields
|
||||
# Fields should be in order in RTL,therefore, use list
|
||||
for field in obj.fields():
|
||||
@ -57,6 +35,15 @@ class Register(Component):
|
||||
|
||||
self.children.append(field_obj)
|
||||
|
||||
# Create generate block for register and add comment
|
||||
self.rtl_header.append("generate")
|
||||
for i in range(self.dimensions):
|
||||
self.rtl_header.append(
|
||||
Register.templ_dict['generate_for_start'].format(
|
||||
iterator = chr(97+i),
|
||||
limit = self.array_dimensions[i]))
|
||||
|
||||
|
||||
# End loops
|
||||
for i in range(self.dimensions-1, -1, -1):
|
||||
self.rtl_footer.append(
|
||||
@ -72,7 +59,7 @@ class Register(Component):
|
||||
rw_wire_assign_field = 'rw_wire_assign_1_dim'
|
||||
|
||||
self.rtl_header.append(
|
||||
Register.templ_dict[rw_wire_assign_field].format(
|
||||
Register.templ_dict[rw_wire_assign_field]['rtl'].format(
|
||||
path = self.path,
|
||||
addr = self.obj.absolute_address,
|
||||
genvars = self.genvars_str,
|
||||
@ -80,6 +67,34 @@ class Register(Component):
|
||||
stride = self.obj.array_stride,
|
||||
depth = self.depth))
|
||||
|
||||
self.yaml_signals_to_list(Register.templ_dict[rw_wire_assign_field])
|
||||
|
||||
# Add wire/register instantiations
|
||||
self.rtl_header = [
|
||||
*[
|
||||
Register.templ_dict['signal_declaration'].format(
|
||||
name = key,
|
||||
type = value[0],
|
||||
unpacked_dim = '[{}]'.format(
|
||||
']['.join(
|
||||
[str(y) for y in value[1]]))
|
||||
if value[1] else '')
|
||||
for (key, value) in self.get_signals().items()],
|
||||
'',
|
||||
*self.rtl_header,
|
||||
]
|
||||
|
||||
# Create comment and provide user information about register he/she
|
||||
# is looking at.
|
||||
self.rtl_header = [
|
||||
Register.templ_dict['reg_comment'].format(
|
||||
name = obj.inst_name,
|
||||
dimensions = self.dimensions,
|
||||
depth = self.depth),
|
||||
*self.rtl_header
|
||||
]
|
||||
|
||||
|
||||
def __process_variables(self, obj: node.RootNode):
|
||||
# Save object
|
||||
self.obj = obj
|
||||
|
||||
@ -11,6 +11,6 @@ module_declaration: |-
|
||||
{outputs}
|
||||
);
|
||||
input_port: |-
|
||||
input {packed_dim:15s}{name:25s} {unpacked_dim},
|
||||
input {signal_type:15s}{name:25s} {unpacked_dim},
|
||||
output_port: |-
|
||||
output {packed_dim:15s}{name:25s} {unpacked_dim},
|
||||
output {signal_type:15s}{name:25s} {unpacked_dim},
|
||||
|
||||
@ -1,80 +1,110 @@
|
||||
---
|
||||
sense_list_rst: |-
|
||||
sense_list_rst:
|
||||
rtl: |-
|
||||
always_ff @(posedge {clk_name} or {rst_edge} {rst_name})
|
||||
sense_list_no_rst: |-
|
||||
sense_list_no_rst:
|
||||
rtl: |-
|
||||
always_ff @(posedge {clk_name})
|
||||
rst_field_assign: |-
|
||||
rst_field_assign:
|
||||
rtl: |-
|
||||
if ({rst_negl}{rst_name})
|
||||
begin
|
||||
{path}_q{genvars} <= {rst_value};
|
||||
end
|
||||
else
|
||||
sw_access_field: |-
|
||||
signals:
|
||||
- name: '{path}_q'
|
||||
signal_type: '{field_type}'
|
||||
sw_access_field:
|
||||
rtl: |-
|
||||
if ({path_wo_field}_sw_wr{genvars})
|
||||
begin
|
||||
sw_access_field_swwe: |-
|
||||
sw_access_field_swwe:
|
||||
rtl: |-
|
||||
if ({path_wo_field}_sw_wr{genvars} && {swwe}) // swwe property
|
||||
begin
|
||||
sw_access_field_swwel: |-
|
||||
sw_access_field_swwel:
|
||||
rtl: |-
|
||||
if ({path_wo_field}_sw_wr{genvars} && !{swwel}) // swwel property
|
||||
begin
|
||||
sw_access_byte: |-
|
||||
sw_access_byte:
|
||||
rtl: |-
|
||||
if (byte_enable[{i}])
|
||||
begin
|
||||
{path}_q{genvars}[{msb_field}-:{field_w}] <= sw_wr_bus[{msb_bus}-:{bus_w}];
|
||||
end
|
||||
|
||||
hw_access_we_wel: |-
|
||||
hw_access_we_wel:
|
||||
rtl: |-
|
||||
if ({negl}{path}_hw_wr{genvars})
|
||||
hw_access_no_we_wel: |-
|
||||
hw_access_no_we_wel:
|
||||
rtl: |-
|
||||
// we or wel property not set
|
||||
hw_access_field: |-
|
||||
hw_access_field:
|
||||
rtl: |-
|
||||
begin
|
||||
{path}_q{genvars} <= {path}_in{genvars};
|
||||
end
|
||||
end_field_ff: |-
|
||||
signals:
|
||||
- name: '{path}_q'
|
||||
signal_type: '{field_type}'
|
||||
input_ports:
|
||||
- name: '{path}_in'
|
||||
signal_type: '{field_type}'
|
||||
end_field_ff:
|
||||
rtl: |-
|
||||
end // of {path}'s always_ff
|
||||
OnWriteType.woset: |-
|
||||
OnWriteType.woset:
|
||||
rtl: |-
|
||||
if (byte_enable[{i}]) // woset property
|
||||
begin
|
||||
{path}_q{genvars}[{msb_field}-:{field_w}] <= {path}_q{genvars}[{msb_field}-:{field_w}] | sw_wr_bus[{msb_bus}-:{bus_w}];
|
||||
end
|
||||
OnWriteType.woclr: |-
|
||||
OnWriteType.woclr:
|
||||
rtl: |-
|
||||
if (byte_enable[{i}]) // woclr property
|
||||
begin
|
||||
{path}_q{genvars}[{msb_field}-:{field_w}] <= {path}_q{genvars}[{msb_field}-:{field_w}] & ~sw_wr_bus[{msb_bus}-:{bus_w}];
|
||||
end
|
||||
OnWriteType.wot: |-
|
||||
OnWriteType.wot:
|
||||
rtl: |-
|
||||
if (byte_enable[{i}]) // wot property
|
||||
begin
|
||||
{path}_q{genvars}[{msb_field}-:{field_w}] <= {path}_q{genvars}[{msb_field}-:{field_w}] ^ sw_wr_bus[{msb_bus}-:{bus_w}];
|
||||
end
|
||||
OnWriteType.wzs: |-
|
||||
OnWriteType.wzs:
|
||||
rtl: |-
|
||||
if (byte_enable[{i}]) // wzs property
|
||||
begin
|
||||
{path}_q{genvars}[{msb_field}-:{field_w}] <= {path}_q{genvars}[{msb_field}-:{field_w}] & sw_wr_bus[{msb_bus}-:{bus_w}];
|
||||
end
|
||||
OnWriteType.wzt: |-
|
||||
OnWriteType.wzt:
|
||||
rtl: |-
|
||||
if (byte_enable[{i}]) // wzt property
|
||||
begin
|
||||
{path}_q{genvars}[{msb_field}-:{field_w}] <= {path}_q{genvars}[{msb_field}-:{field_w}] ~^ sw_wr_bus[{msb_bus}-:{bus_w}];
|
||||
end
|
||||
OnWriteType.wclr: |-
|
||||
OnWriteType.wclr:
|
||||
rtl: |-
|
||||
{path}_q{genvars} <= {{width{{1'b0}}}};
|
||||
OnWriteType.wset: |-
|
||||
OnWriteType.wset:
|
||||
rtl: |-
|
||||
{path}_q{genvars} <= {{width{{1'b1}}}};
|
||||
OnReadType.rclr: |-
|
||||
OnReadType.rclr:
|
||||
rtl: |-
|
||||
if ({path_wo_field}_sw_rd{genvars}) // rclr property
|
||||
begin
|
||||
{path}_q{genvars} <= {{width{{1'b0}}}};
|
||||
end
|
||||
OnReadType.rset: |-
|
||||
OnReadType.rset:
|
||||
rtl: |-
|
||||
if ({path_wo_field}_sw_rd{genvars}) // rset property
|
||||
begin
|
||||
{path}_q{genvars} <= {{width{{1'b1}}}};
|
||||
end
|
||||
|
||||
field_comment: |-
|
||||
field_comment:
|
||||
rtl: |-
|
||||
|
||||
//-----------------FIELD SUMMARY-----------------
|
||||
// name : {name} ({path_wo_field}[{msb}:{lsb}])
|
||||
@ -83,17 +113,80 @@ field_comment: |-
|
||||
// reset : {rst_active} / {rst_type}
|
||||
// flags : {misc_flags}
|
||||
//-----------------------------------------------
|
||||
combo_operation_comment: |-
|
||||
combo_operation_comment:
|
||||
rtl: |-
|
||||
|
||||
// Combinational logic for {path}
|
||||
assign_combo_operation: |-
|
||||
assign {path}_{op_name}{genvars} = {op_verilog}{path}_q{genvars}
|
||||
singlepulse: |-
|
||||
assign_anded_operation:
|
||||
rtl: |-
|
||||
assign {path}_anded{genvars} = {op_verilog}{path}_q{genvars};
|
||||
output_ports:
|
||||
- name: '{path}_anded'
|
||||
signal_type: 'logic'
|
||||
assign_ored_operation:
|
||||
rtl: |-
|
||||
assign {path}_ored{genvars} = {op_verilog}{path}_q{genvars};
|
||||
output_ports:
|
||||
- name: '{path}_ored'
|
||||
signal_type: 'logic'
|
||||
assign_xored_operation:
|
||||
rtl: |-
|
||||
assign {path}_xored{genvars} = {op_verilog}{path}_q{genvars};
|
||||
output_ports:
|
||||
- name: '{path}_xored'
|
||||
signal_type: 'logic'
|
||||
singlepulse:
|
||||
rtl: |-
|
||||
begin
|
||||
{path}{genvars} <= 0;
|
||||
{path}{genvars}_q <= 0;
|
||||
end
|
||||
out_port_assign: |-
|
||||
|
||||
out_port_assign:
|
||||
rtl: |-
|
||||
// Connect register to hardware output port
|
||||
assign {path}_r{genvars} = {path}_q{genvars};
|
||||
output_ports:
|
||||
- name: '{path}_r'
|
||||
signal_type: '{field_type}'
|
||||
counter:
|
||||
rtl: |-
|
||||
always_comb
|
||||
begin
|
||||
{path}_next{genvars} = {path}_q{genvars};
|
||||
{path}_update_cnt{genvars} = 0;
|
||||
|
||||
{incr_counter}
|
||||
|
||||
{decr_counter}
|
||||
end
|
||||
incr_counter:
|
||||
rtl: |-
|
||||
{incr_counter_condition}
|
||||
begin
|
||||
{path}_next{genvars} += {path}_{operation_str}_val{genvars};
|
||||
{path}_update_cnt{genvars} = 1;
|
||||
end
|
||||
decr_counter:
|
||||
rtl: |-
|
||||
{incr_counter_condition}
|
||||
begin
|
||||
{path}_next{genvars} += {path}_{operation_str}_val{genvars};
|
||||
{path}_update_cnt{genvars} = 1;
|
||||
end
|
||||
incr_counter_condition:
|
||||
rtl: |-
|
||||
if ({path}_incr{genvars})
|
||||
incr_sat_counter_condition:
|
||||
rtl: |-
|
||||
if ({path}_incr{genvars} && {path}_next{genvars} + {path}_incr_val{genvars} <= {sat_value})
|
||||
decr_counter_condition:
|
||||
rtl: |-
|
||||
if ({path}_decr{genvars})
|
||||
decr_sat_counter_condition:
|
||||
rtl: |-
|
||||
if ({path}_decr{genvars} && {path}_next{genvars} - {path}_decr_val{genvars} >= {sat_value})
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@ -1,14 +1,39 @@
|
||||
---
|
||||
rw_wire_declare: |
|
||||
logic {path}_sw_wr {depth};
|
||||
logic {path}_sw_rd {depth};
|
||||
rw_wire_assign_1_dim: |
|
||||
assign {path}_sw_wr{genvars} = addr == {addr} && r_vld;
|
||||
assign {path}_sw_rd{genvars} = addr == {addr} && w_vld;
|
||||
rw_wire_assign_multi_dim: |
|
||||
assign {path}_sw_wr{genvars} = addr == ({addr}+({genvars_sum})*{stride}) && r_vld;
|
||||
assign {path}_sw_rd{genvars} = addr == ({addr}+({genvars_sum})*{stride}) && w_vld;
|
||||
rw_wire_assign_1_dim:
|
||||
rtl: |
|
||||
// Assign register-activation signals
|
||||
assign {path}_reg_active{genvars} = addr == {addr};
|
||||
|
||||
assign {path}_sw_wr = {path}_reg_active && r_vld;
|
||||
assign {path}_sw_rd = {path}_reg_active && w_vld;
|
||||
signals:
|
||||
- name: '{path}_sw_wr'
|
||||
signal_type: 'logic'
|
||||
- name: '{path}_sw_rd'
|
||||
signal_type: 'logic'
|
||||
- name: '{path}_reg_active'
|
||||
signal_type: 'logic'
|
||||
input_ports:
|
||||
output_ports:
|
||||
rw_wire_assign_multi_dim:
|
||||
rtl: |
|
||||
|
||||
// Assign register-activation signals
|
||||
assign {path}_reg_active{genvars} = addr == ({addr}+({genvars_sum})*{stride});
|
||||
|
||||
assign {path}_sw_wr{genvars} = {path}_reg_active{genvars} && r_vld;
|
||||
assign {path}_sw_rd{genvars} = {path}_reg_active{genvars} && w_vld;
|
||||
signals:
|
||||
- name: '{path}_sw_wr'
|
||||
signal_type: 'logic'
|
||||
- name: '{path}_sw_rd'
|
||||
signal_type: 'logic'
|
||||
- name: '{path}_reg_active'
|
||||
signal_type: 'logic'
|
||||
input_ports:
|
||||
output_ports:
|
||||
reg_comment: |-
|
||||
|
||||
/*******************************************************************
|
||||
*******************************************************************
|
||||
* REGISTER : {name}
|
||||
@ -21,3 +46,5 @@ generate_for_start: |-
|
||||
begin
|
||||
generate_for_end: |-
|
||||
end // of for loop with iterator {dimension}
|
||||
signal_declaration: |-
|
||||
{type:10s}{name:20s} {unpacked_dim};
|
||||
|
||||
Loading…
Reference in New Issue
Block a user