Dennis/srdl2sv
1
0
Fork 0
mirror of https://github.com/Silicon1602/srdl2sv.git synced 2024-11-14 03:03:35 +00:00
Code Issues Projects Releases Wiki Activity

Add incrthreshold/decrthreshold support

Browse Source 
It is still not possible to assign overflow/threshold signals to any
input of a different register!
This commit is contained in:
Dennis Potter 2021-06-29 00:14:51 +02:00
parent 18204d9a3e
commit 1d50b2b457
Signed by: Dennis
GPG Key ID: 186A8AD440942BAF
2 changed files with 64 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

49
srdl2sv/components/field.py
View File

@ -214,7 +214,7 @@ class Field(Component):
self.rtl_footer.append(Field.templ_dict['counter_comment']['rtl'])
# Determine saturation values and add appropriate RTL
# Determine saturation values
if isinstance(self.obj.get_property('incrsaturate'), bool):
if self.obj.get_property('incrsaturate'):
incr_sat_value = 2**self.obj.width-1
@ -237,6 +237,23 @@ class Field(Component):
decr_sat_value = self.obj.get_property('decrsaturate')
underflow_value = decr_sat_value
# Determine threshold values
if isinstance(self.obj.get_property('incrthreshold'), bool):
if self.obj.get_property('incrthreshold'):
incr_thr_value = 2**self.obj.width-1
else:
incr_thr_value = False
else:
incr_thr_value = self.obj.get_property('incrthreshold')
if isinstance(self.obj.get_property('decrthreshold'), bool):
if self.obj.get_property('decrthreshold'):
decr_thr_value = 2**self.obj.width-1
else:
decr_thr_value = False
else:
decr_thr_value = self.obj.get_property('decrthreshold')
# Determine with what value the counter is incremented
# According to the spec, the incrvalue/decrvalue default to '1'
obj_incr_value = self.obj.get_property('incrvalue')
@ -508,6 +525,36 @@ class Field(Component):
)
)
# Handle threshold values
if incr_thr_value or decr_thr_value:
self.rtl_footer.append(Field.templ_dict['counter_thr_comment']['rtl'])
if incr_thr_value:
self.rtl_footer.append(
self.process_yaml(
Field.templ_dict['counter_incr_thr'],
{'path': self.path_underscored,
'genvars': self.genvars_str,
'incr_width': incr_width,
'decr_width': decr_width,
'thr_value': incr_thr_value,
}
)
)
if decr_thr_value:
self.rtl_footer.append(
self.process_yaml(
Field.templ_dict['counter_decr_thr'],
{'path': self.path_underscored,
'genvars': self.genvars_str,
'incr_width': incr_width,
'decr_width': decr_width,
'thr_value': decr_thr_value,
}
)
)
# Handle overflow & underflow signals
if self.obj.get_property('overflow'):
self.rtl_footer.append(

16
srdl2sv/components/templates/fields.yaml
View File

@ -344,6 +344,22 @@ counter_decr_sat_tied:
signals:
- name: '{path}_decr_sat'
signal_type: 'logic'
counter_thr_comment:
rtl: |-
// Define threshold signals (similar to overflow, but for a user specified value)
counter_incr_thr:
rtl: |-
assign {path}_incr_thr{genvars} = {path}_q{genvars} + ({{{incr_width}{{{path}_incr}}}} & {path}_incr_val) - ({{{decr_width}{{{path}_decr}}}} & {path}_decr_val) > {thr_value};
output_ports:
- name: '{path}_incr_thr'
signal_type: 'logic'
counter_decr_thr:
rtl: |-
assign {path}_decr_thr{genvars} = {path}_q{genvars} + ({{{incr_width}{{{path}_incr}}}} & {path}_incr_val) - ({{{decr_width}{{{path}_decr}}}} & {path}_decr_val) > {thr_value};
output_ports:
- name: '{path}_decr_thr'
signal_type: 'logic'
counter_overflow:
rtl: |-