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https://github.com/Silicon1602/srdl2sv.git
synced 2024-11-14 03:03:35 +00:00
Add support for field_reset and cpuif_reset
These two special kind of resets are now recognized by the compiler and are propagated to all regfiles, registers, and fields. Furthermore, every object has a set of resets which will be used to generate a seperate input section for resets in the addrmap.
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@ -29,15 +29,22 @@ class AddrMap(Component):
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template = pkg_resources.read_text(templates, 'addrmap.sv')
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# Check if global resets are defined
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glbl_settings = dict()
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(glbl_settings['field_reset'], glbl_settings['cpuif_reset']) = \
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self.__process_global_resets()
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# Empty dictionary of register objects
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# We need a dictionary since it might be required to access the objects later
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# by name (for example, in case of aliases)
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self.registers = dict()
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self.rdl_nodes = dict()
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# Traverse through children
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for child in obj.children():
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if isinstance(child, node.AddrmapNode):
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# This addressmap opens a completely new scope. For example,
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# a field_reset does not propagate through to this scope.
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self.logger.info('Found hierarchical addrmap. Entering it...')
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self.logger.error('Child addrmaps are not implemented yet!')
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elif isinstance(child, node.RegfileNode):
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@ -49,7 +56,8 @@ class AddrMap(Component):
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# additional properties
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self.logger.error('Alias registers are not implemented yet!')
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else:
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self.registers[child.inst_name] = Register(child, config)
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self.registers[child.inst_name] = \
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Register(child, config, glbl_settings)
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# Add regfiles and registers to children
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self.children = [x for x in self.registers.values()]
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@ -59,6 +67,13 @@ class AddrMap(Component):
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# Start assembling addrmap module
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self.logger.info("Starting to assemble input/output/inout ports")
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# Reset ports
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reset_ports_rtl = [
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AddrMap.templ_dict['reset_port'].format(
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name = name)
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for name in [x for x in self.get_resets()]
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]
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# Prefetch dictionaries in local array
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input_dict_list = [(key, value) for (key, value) in self.get_ports('input').items()]
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output_dict_list = [(key, value) for (key, value) in self.get_ports('output').items()]
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@ -110,6 +125,7 @@ class AddrMap(Component):
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self.rtl_header.append(
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AddrMap.templ_dict['module_declaration'].format(
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name = obj.inst_name,
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resets = '\n'.join(reset_ports_rtl),
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inputs = '\n'.join(input_ports_rtl),
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outputs = '\n'.join(output_ports_rtl)))
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@ -126,3 +142,43 @@ class AddrMap(Component):
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self.path_underscored = self.path.replace('.', '_')
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self.name = obj.inst_name
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def __process_global_resets(self):
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field_reset_list = \
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[x for x in self.obj.signals() if x.get_property('field_reset')]
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cpuif_reset_list = \
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[x for x in self.obj.signals() if x.get_property('cpuif_reset')]
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if field_reset_list:
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rst_name = field_reset_list[0].inst_name
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self.logger.info("Found field_reset signal '{}'".format(rst_name))
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# Save to set to generate input
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self.resets.add(rst_name)
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# Save position 0 of list
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field_reset_item = field_reset_list[0]
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else:
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field_reset_item = None
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if cpuif_reset_list:
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rst_name = cpuif_reset_list[0].inst_name
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self.logger.info("Found cpuif_reset signal '{}'".format(rst_name))
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# Save to set to generate input
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self.resets.add(rst_name)
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# Save position 0 of list
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cpuif_reset_item = cpuif_reset_list[0]
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else:
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cpuif_reset_item = None
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# Method is only called once on a global level. Otherwise, process_reset_signal
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# is called several times to calculate the dictionary, although it will always
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# return the same result.
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field_reset = AddrMap.process_reset_signal(field_reset_item)
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cpuif_reset = AddrMap.process_reset_signal(cpuif_reset_item)
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return (field_reset, cpuif_reset)
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@ -18,6 +18,7 @@ class Component():
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self.children = []
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self.typedef = dict()
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self.ports = dict()
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self.resets = set()
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self.signals = dict()
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self.ports['input'] = dict()
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self.ports['output'] = dict()
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@ -31,6 +32,14 @@ class Component():
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file_name=config['file_log_location'])
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self.logger.propagate = False
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def get_resets(self):
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self.logger.debug("Return reset list")
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for x in self.children:
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self.resets |= x.get_resets()
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return self.resets
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def get_ports(self, port_type: str):
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self.logger.debug("Return port list")
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@ -169,3 +178,29 @@ class Component():
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self.array_dimensions)
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except (TypeError, KeyError):
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pass
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@staticmethod
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def process_reset_signal(reset_signal):
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rst = dict()
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try:
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rst['name'] = reset_signal.inst_name
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rst['async'] = reset_signal.get_property("async")
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rst['type'] = "asynchronous" if rst['async'] else "synchronous"
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# Active low or active high?
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if reset_signal.get_property("activelow"):
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rst['edge'] = "negedge"
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rst['active'] = "active_low"
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else:
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rst['edge'] = "posedge"
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rst['active'] = "active_high"
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except:
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rst['async'] = False
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rst['name'] = None
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rst['edge'] = None
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rst['value'] = "'x"
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rst['active'] = "-"
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rst['type'] = "-"
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return rst
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@ -16,11 +16,11 @@ class Field(Component):
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pkg_resources.read_text(templates, 'fields.yaml'),
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Loader=yaml.FullLoader)
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def __init__(self, obj: FieldNode, array_dimensions: list, config:dict):
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def __init__(self, obj: FieldNode, array_dimensions: list, config:dict, glbl_settings: dict):
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super().__init__()
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# Save and/or process important variables
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self.__process_variables(obj, array_dimensions)
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self.__process_variables(obj, array_dimensions, glbl_settings)
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# Create logger object
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self.create_logger("{}.{}".format(self.owning_addrmap, self.path), config)
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@ -136,7 +136,7 @@ class Field(Component):
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else:
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self.field_type = 'logic'
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def __process_variables(self, obj: FieldNode, array_dimensions: list):
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def __process_variables(self, obj: FieldNode, array_dimensions: list, glbl_settings: dict):
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# Save object
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self.obj = obj
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@ -168,32 +168,22 @@ class Field(Component):
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# the reset value, and whether the field actually has a reset
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self.rst = dict()
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try:
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rst_signal = obj.get_property("resetsignal")
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reset_signal = obj.get_property("resetsignal")
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self.rst['name'] = rst_signal.inst_name
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self.rst['async'] = rst_signal.get_property("async")
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self.rst['type'] = "asynchronous" if self.rst['async'] else "synchronous"
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# Active low or active high?
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if rst_signal.get_property("activelow"):
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self.rst['edge'] = "negedge"
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self.rst['active'] = "active_low"
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if (reset_signal):
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self.rst = Field.process_reset_signal(reset_signal)
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else:
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self.rst['edge'] = "posedge"
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self.rst['active'] = "active_high"
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# Only use global reset (if present) if no local reset is set
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self.rst = glbl_settings['field_reset']
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# Value of reset?
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self.rst['value'] = '\'x' if obj.get_property("reset") == None else\
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self.resets.add(self.rst['name'])
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# Value of reset must always be determined on field level
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self.rst['value'] = \
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'\'x' if obj.get_property("reset") == None else\
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obj.get_property('reset')
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except:
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self.rst['async'] = False
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self.rst['name'] = None
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self.rst['edge'] = None
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self.rst['value'] = "'x"
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self.rst['active'] = "-"
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self.rst['type'] = "-"
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# Define hardware access
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self.hw_access = obj.get_property('hw')
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self.sw_access = obj.get_property('sw')
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self.precedence = obj.get_property('precedence')
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@ -1,8 +1,7 @@
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import importlib.resources as pkg_resources
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import yaml
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from systemrdl import RDLCompiler, RDLCompileError, RDLWalker, RDLListener, node
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from systemrdl.node import FieldNode
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from systemrdl import node
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# Local modules
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from components.component import Component
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@ -15,7 +14,7 @@ class Register(Component):
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pkg_resources.read_text(templates, 'regs.yaml'),
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Loader=yaml.FullLoader)
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def __init__(self, obj: node.RootNode, config: dict):
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def __init__(self, obj: node.RootNode, config: dict, glbl_settings: dict):
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super().__init__()
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# Save and/or process important variables
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@ -28,7 +27,7 @@ class Register(Component):
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# Create RTL for fields
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# Fields should be in order in RTL,therefore, use list
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for field in obj.fields():
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field_obj = Field(field, self.array_dimensions, config)
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field_obj = Field(field, self.array_dimensions, config, glbl_settings)
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if not config['disable_sanity']:
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field_obj.sanity_checks()
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@ -1,6 +1,11 @@
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---
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module_declaration: |-
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module {name} (
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// Clock & Resets
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input reg_clk,
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input bus_clk,
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{resets}
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// Bus I/O
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// TODO
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@ -10,6 +15,8 @@ module_declaration: |-
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// Outputs
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{outputs}
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);
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reset_port: |-
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input {name},
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input_port: |-
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input {signal_type:{signal_width}} {name:{name_width}}{unpacked_dim},
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output_port: |-
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