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A SystemRDL 2.0 to (synthesizable) SystemVerilog compiler.
20 Commits 1 Branch 0 Tags 713 KiB
Python 92.9%
SystemVerilog 5.7%
Makefile 1.4%
2a3cc9505e
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Dennis 2a3cc9505e
Add support for field_reset and cpuif_reset 
These two special kind of resets are now recognized by the compiler and
are propagated to all regfiles, registers, and fields.

Furthermore, every object has a set of resets which will be used to
generate a seperate input section for resets in the addrmap.
2021-05-24 14:42:24 +02:00
srdl2sv Add support for field_reset and cpuif_reset 2021-05-24 14:42:24 +02:00
.gitignore Initial commit of SRDL2SV 2021-05-02 00:58:43 +02:00
LIMITATIONS.md Initial commit of SRDL2SV 2021-05-02 00:58:43 +02:00