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Update examples with changes from ae83dceb
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99
examples/aliases/log
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99
examples/aliases/log
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@ -0,0 +1,99 @@
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verilator -cc -sv srdl2sv_out/aliases.sv srdl2sv_out/srdl2sv_amba3ahblite.sv srdl2sv_out/srdl2sv_widget_if.sv
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%Error: srdl2sv_out/aliases.sv:103:25: Duplicate declaration of signal: 'example_rf__ext_main_reg__f1_ext_w_ack'
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103 | input example_rf__ext_main_reg__f1_ext_w_ack [4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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srdl2sv_out/aliases.sv:98:25: ... Location of original declaration
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98 | input example_rf__ext_main_reg__f1_ext_w_ack[4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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%Error: srdl2sv_out/aliases.sv:104:25: Duplicate declaration of signal: 'example_rf__ext_main_reg__f1_ext_w_err'
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104 | input example_rf__ext_main_reg__f1_ext_w_err [4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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srdl2sv_out/aliases.sv:97:25: ... Location of original declaration
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97 | input example_rf__ext_main_reg__f1_ext_w_err[4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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%Error: srdl2sv_out/aliases.sv:109:25: Duplicate declaration of signal: 'example_rf__ext_main_reg__f1_ext_r_ack'
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109 | input example_rf__ext_main_reg__f1_ext_r_ack [4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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srdl2sv_out/aliases.sv:94:25: ... Location of original declaration
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94 | input example_rf__ext_main_reg__f1_ext_r_ack[4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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%Error: srdl2sv_out/aliases.sv:110:25: Duplicate declaration of signal: 'example_rf__ext_main_reg__f1_ext_r_err'
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110 | input example_rf__ext_main_reg__f1_ext_r_err [4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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srdl2sv_out/aliases.sv:93:25: ... Location of original declaration
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93 | input example_rf__ext_main_reg__f1_ext_r_err[4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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%Error: srdl2sv_out/aliases.sv:118:25: Duplicate declaration of signal: 'example_rf__ext_main_reg__f2_ext_w_ack'
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118 | input example_rf__ext_main_reg__f2_ext_w_ack [4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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srdl2sv_out/aliases.sv:100:25: ... Location of original declaration
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100 | input example_rf__ext_main_reg__f2_ext_w_ack[4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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%Error: srdl2sv_out/aliases.sv:119:25: Duplicate declaration of signal: 'example_rf__ext_main_reg__f2_ext_w_err'
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119 | input example_rf__ext_main_reg__f2_ext_w_err [4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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srdl2sv_out/aliases.sv:99:25: ... Location of original declaration
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99 | input example_rf__ext_main_reg__f2_ext_w_err[4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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%Error: srdl2sv_out/aliases.sv:124:25: Duplicate declaration of signal: 'example_rf__ext_main_reg__f2_ext_r_ack'
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124 | input example_rf__ext_main_reg__f2_ext_r_ack [4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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srdl2sv_out/aliases.sv:96:25: ... Location of original declaration
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96 | input example_rf__ext_main_reg__f2_ext_r_ack[4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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%Error: srdl2sv_out/aliases.sv:125:25: Duplicate declaration of signal: 'example_rf__ext_main_reg__f2_ext_r_err'
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125 | input example_rf__ext_main_reg__f2_ext_r_err [4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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srdl2sv_out/aliases.sv:95:25: ... Location of original declaration
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95 | input example_rf__ext_main_reg__f2_ext_r_err[4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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%Error: srdl2sv_out/aliases.sv:103:25: Duplicate declaration of port: 'example_rf__ext_main_reg__f1_ext_w_ack'
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103 | input example_rf__ext_main_reg__f1_ext_w_ack [4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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srdl2sv_out/aliases.sv:98:25: ... Location of original declaration
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98 | input example_rf__ext_main_reg__f1_ext_w_ack[4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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%Error: srdl2sv_out/aliases.sv:104:25: Duplicate declaration of port: 'example_rf__ext_main_reg__f1_ext_w_err'
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104 | input example_rf__ext_main_reg__f1_ext_w_err [4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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srdl2sv_out/aliases.sv:97:25: ... Location of original declaration
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97 | input example_rf__ext_main_reg__f1_ext_w_err[4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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%Error: srdl2sv_out/aliases.sv:109:25: Duplicate declaration of port: 'example_rf__ext_main_reg__f1_ext_r_ack'
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109 | input example_rf__ext_main_reg__f1_ext_r_ack [4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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srdl2sv_out/aliases.sv:94:25: ... Location of original declaration
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94 | input example_rf__ext_main_reg__f1_ext_r_ack[4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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%Error: srdl2sv_out/aliases.sv:110:25: Duplicate declaration of port: 'example_rf__ext_main_reg__f1_ext_r_err'
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110 | input example_rf__ext_main_reg__f1_ext_r_err [4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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srdl2sv_out/aliases.sv:93:25: ... Location of original declaration
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93 | input example_rf__ext_main_reg__f1_ext_r_err[4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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%Error: srdl2sv_out/aliases.sv:118:25: Duplicate declaration of port: 'example_rf__ext_main_reg__f2_ext_w_ack'
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118 | input example_rf__ext_main_reg__f2_ext_w_ack [4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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srdl2sv_out/aliases.sv:100:25: ... Location of original declaration
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100 | input example_rf__ext_main_reg__f2_ext_w_ack[4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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%Error: srdl2sv_out/aliases.sv:119:25: Duplicate declaration of port: 'example_rf__ext_main_reg__f2_ext_w_err'
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119 | input example_rf__ext_main_reg__f2_ext_w_err [4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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srdl2sv_out/aliases.sv:99:25: ... Location of original declaration
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99 | input example_rf__ext_main_reg__f2_ext_w_err[4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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%Error: srdl2sv_out/aliases.sv:124:25: Duplicate declaration of port: 'example_rf__ext_main_reg__f2_ext_r_ack'
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124 | input example_rf__ext_main_reg__f2_ext_r_ack [4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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srdl2sv_out/aliases.sv:96:25: ... Location of original declaration
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96 | input example_rf__ext_main_reg__f2_ext_r_ack[4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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%Error: srdl2sv_out/aliases.sv:125:25: Duplicate declaration of port: 'example_rf__ext_main_reg__f2_ext_r_err'
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125 | input example_rf__ext_main_reg__f2_ext_r_err [4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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srdl2sv_out/aliases.sv:95:25: ... Location of original declaration
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95 | input example_rf__ext_main_reg__f2_ext_r_err[4],
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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%Error: Exiting due to 16 error(s)
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make: *** [Makefile:8: verilog_compile] Error 1
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@ -20,7 +20,7 @@
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*
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* Generation information:
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* - User: : dpotter
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* - Time : November 07 2021 11:34:07
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* - Time : November 26 2021 16:31:40
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* - Path : /home/dpotter/srdl2sv/examples/aliases
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* - RDL file : ['aliases.rdl']
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* - Hostname : ArchXPS
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@ -70,11 +70,13 @@
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module aliases
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(
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// Resets
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// Reset signals declared for registers
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// Inputs
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input clk ,
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// Ports for 'General Clock'
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input clk,
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// Ports for 'AHB Protocol'
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input HRESETn ,
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input [31:0] HADDR ,
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input HWRITE ,
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@ -83,6 +85,11 @@ module aliases
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input [1:0] HTRANS ,
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input [32-1:0] HWDATA ,
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input HSEL ,
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output HREADYOUT,
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output HRESP ,
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output [32-1:0] HRDATA ,
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// Ports for 'example_rf__ext_main_reg'
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input example_rf__ext_main_reg__f1_ext_r_err [4],
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input example_rf__ext_main_reg__f1_ext_r_ack [4],
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input example_rf__ext_main_reg__f2_ext_r_err [4],
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@ -91,40 +98,40 @@ module aliases
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input example_rf__ext_main_reg__f1_ext_w_ack [4],
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input example_rf__ext_main_reg__f2_ext_w_err [4],
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input example_rf__ext_main_reg__f2_ext_w_ack [4],
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input [15:0] example_rf__ext_main_reg__f1_ext_r_data[4],
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input [15:0] example_rf__ext_main_reg__f2_ext_r_data[4],
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input [0:0] event1__some_event_in ,
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input four_field_reg__f1_hw_wr ,
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input [7:0] four_field_reg__f1_in ,
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input four_field_reg__f2_hw_wr ,
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input [7:0] four_field_reg__f2_in ,
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input four_field_reg__f3_hw_wr ,
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input [7:0] four_field_reg__f3_in ,
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input four_field_reg__f4_hw_wr ,
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input [7:0] four_field_reg__f4_in ,
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// Outputs
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output HREADYOUT ,
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output HRESP ,
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output [32-1:0] HRDATA ,
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output example_rf__ext_main_reg__f1_ext_w_req [4],
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output [15:0] example_rf__ext_main_reg__f1_ext_w_data [4],
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output [15:0] example_rf__ext_main_reg__f1_ext_w_mask [4],
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input [15:0] example_rf__ext_main_reg__f1_ext_r_data [4],
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output example_rf__ext_main_reg__f1_ext_r_req [4],
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output example_rf__ext_alias_reg__field_1_ext_w_req[4],
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output example_rf__ext_alias_reg__field_1_ext_w_req [4],
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output [15:0] example_rf__ext_alias_reg__field_1_ext_w_data[4],
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output [15:0] example_rf__ext_alias_reg__field_1_ext_w_mask[4],
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output example_rf__ext_alias_reg__field_1_ext_r_req[4],
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output example_rf__ext_alias_reg__field_1_ext_r_req [4],
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output example_rf__ext_main_reg__f2_ext_w_req [4],
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output [15:0] example_rf__ext_main_reg__f2_ext_w_data [4],
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output [15:0] example_rf__ext_main_reg__f2_ext_w_mask [4],
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input [15:0] example_rf__ext_main_reg__f2_ext_r_data [4],
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output example_rf__ext_main_reg__f2_ext_r_req [4],
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// Ports for 'event1'
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output event1_intr ,
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input [0:0] event1__some_event_in,
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// Ports for 'four_field_reg'
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input four_field_reg__f1_hw_wr,
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input [7:0] four_field_reg__f1_in ,
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output [7:0] four_field_reg__f1_r ,
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input four_field_reg__f2_hw_wr,
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input [7:0] four_field_reg__f2_in ,
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output [7:0] four_field_reg__f2_r ,
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input four_field_reg__f3_hw_wr,
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input [7:0] four_field_reg__f3_in ,
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output [7:0] four_field_reg__f3_r ,
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output reg four_field_reg__f3_swmod ,
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output reg four_field_reg__f3_swmod,
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input four_field_reg__f4_hw_wr,
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input [7:0] four_field_reg__f4_in ,
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output [7:0] four_field_reg__f4_r
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);
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@ -20,7 +20,7 @@
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*
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* Generation information:
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* - User: : dpotter
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* - Time : November 17 2021 22:15:57
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* - Time : November 26 2021 16:32:56
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* - Path : /home/dpotter/srdl2sv/examples/counters
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* - RDL file : ['counters.rdl']
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* - Hostname : ArchXPS
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@ -70,11 +70,13 @@
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module counters
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(
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// Resets
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// Reset signals declared for registers
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input rst_async_n,
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// Inputs
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input clk ,
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// Ports for 'General Clock'
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input clk,
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// Ports for 'AHB Protocol'
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input HRESETn ,
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input [31:0] HADDR ,
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input HWRITE ,
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@ -83,23 +85,30 @@ module counters
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input [1:0] HTRANS ,
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input [32-1:0] HWDATA ,
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input HSEL ,
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input wide_counters__counter_b_lsb__cnt_incr[2],
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input counter_a__cnt_hwclr ,
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input counter_a__cnt_incr ,
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input counter_a__cnt_decr ,
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// Outputs
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output HREADYOUT ,
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output HREADYOUT,
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output HRESP ,
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output [32-1:0] HRDATA ,
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// Ports for 'wide_counters__counter_b_lsb'
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output [31:0] wide_counters__counter_b_lsb__cnt_r [2],
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input wide_counters__counter_b_lsb__cnt_incr [2],
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output wide_counters__counter_b_lsb__cnt_overflow[2],
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// Ports for 'wide_counters__counter_b_msb'
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output [31:0] wide_counters__counter_b_msb__cnt_r [2],
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output wide_counters__counter_b_msb__cnt_overflow[2],
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// Ports for 'counter_a'
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input counter_a__cnt_hwclr ,
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output [31:0] counter_a__cnt_r ,
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output counter_a__cnt_incr_thr ,
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output counter_a__cnt_overflow ,
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input counter_a__cnt_incr ,
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input counter_a__cnt_decr ,
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output counter_a__cnt_incr_thr,
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output counter_a__cnt_overflow,
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// Ports for 'counter_b_overflow_intr'
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output counter_b_overflow_intr_intr
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);
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/*******************************************************************
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@ -163,34 +172,34 @@ that will fire an interrupt as soon as it wraps around.
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// Variables of register 'counter_b_lsb'
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logic wide_counters__counter_b_lsb_active [2];
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logic wide_counters__counter_b_lsb_sw_wr [2];
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logic [31:0] wide_counters__counter_b_lsb_data_mux_in[2];
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logic [31:0] wide_counters__counter_b_lsb_data_mux_in [2];
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logic wide_counters__counter_b_lsb_rdy_mux_in [2];
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logic wide_counters__counter_b_lsb_err_mux_in [2];
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logic [31:0] wide_counters__counter_b_lsb__cnt_q [2];
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logic wide_counters__counter_b_lsb__cnt_update_cnt[2];
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logic wide_counters__counter_b_lsb__cnt_update_cnt [2];
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logic [31:0] wide_counters__counter_b_lsb__cnt_next [2];
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logic [0:0] wide_counters__counter_b_lsb__cnt_incr_val[2];
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logic [0:0] wide_counters__counter_b_lsb__cnt_decr_val[2];
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logic [0:0] wide_counters__counter_b_lsb__cnt_incr_val [2];
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logic [0:0] wide_counters__counter_b_lsb__cnt_decr_val [2];
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logic wide_counters__counter_b_lsb__cnt_decr [2];
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logic wide_counters__counter_b_lsb__cnt_incr_sat[2];
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logic wide_counters__counter_b_lsb__cnt_decr_sat[2];
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logic wide_counters__counter_b_lsb__cnt_incr_sat [2];
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logic wide_counters__counter_b_lsb__cnt_decr_sat [2];
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logic wide_counters__counter_b_lsb__cnt_overflow_int[2];
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// Variables of register 'counter_b_msb'
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logic wide_counters__counter_b_msb_active [2];
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logic wide_counters__counter_b_msb_sw_wr [2];
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logic [31:0] wide_counters__counter_b_msb_data_mux_in[2];
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logic [31:0] wide_counters__counter_b_msb_data_mux_in [2];
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logic wide_counters__counter_b_msb_rdy_mux_in [2];
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logic wide_counters__counter_b_msb_err_mux_in [2];
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logic [31:0] wide_counters__counter_b_msb__cnt_q [2];
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logic wide_counters__counter_b_msb__cnt_update_cnt[2];
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logic wide_counters__counter_b_msb__cnt_update_cnt [2];
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logic [31:0] wide_counters__counter_b_msb__cnt_next [2];
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logic [0:0] wide_counters__counter_b_msb__cnt_incr_val[2];
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logic [0:0] wide_counters__counter_b_msb__cnt_decr_val[2];
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logic [0:0] wide_counters__counter_b_msb__cnt_incr_val [2];
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logic [0:0] wide_counters__counter_b_msb__cnt_decr_val [2];
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logic wide_counters__counter_b_msb__cnt_incr [2];
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logic wide_counters__counter_b_msb__cnt_decr [2];
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logic wide_counters__counter_b_msb__cnt_incr_sat[2];
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logic wide_counters__counter_b_msb__cnt_decr_sat[2];
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logic wide_counters__counter_b_msb__cnt_incr_sat [2];
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logic wide_counters__counter_b_msb__cnt_decr_sat [2];
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logic wide_counters__counter_b_msb__cnt_overflow_int[2];
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generate
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@ -20,7 +20,7 @@
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*
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||||
* Generation information:
|
||||
* - User: : dpotter
|
||||
* - Time : November 02 2021 23:27:37
|
||||
* - Time : November 26 2021 16:32:56
|
||||
* - Path : /home/dpotter/srdl2sv/examples/enums
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* - RDL file : ['enums.rdl']
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* - Hostname : ArchXPS
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||||
@ -35,6 +35,7 @@
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* - Use Real Tabs : False
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* - Tab Width : 4
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* - Enums Enabled : True
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* - Address Errors : True
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* - Unpacked I/Os : True
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* - Register Bus Type: amba3ahblite
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* - Address width : 32
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@ -70,11 +71,13 @@ module enums
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import enums_pkg::*;
|
||||
import enums__regfile_1_pkg::*;
|
||||
(
|
||||
// Resets
|
||||
// Reset signals declared for registers
|
||||
|
||||
|
||||
// Inputs
|
||||
input clk ,
|
||||
// Ports for 'General Clock'
|
||||
input clk,
|
||||
|
||||
// Ports for 'AHB Protocol'
|
||||
input HRESETn ,
|
||||
input [31:0] HADDR ,
|
||||
input HWRITE ,
|
||||
@ -83,27 +86,34 @@ module enums
|
||||
input [1:0] HTRANS ,
|
||||
input [32-1:0] HWDATA ,
|
||||
input HSEL ,
|
||||
input enums_pkg::third_enum regfile_1__reg_c__f1_in,
|
||||
input [1:0] regfile_1__reg_c__f2_in,
|
||||
input enums__regfile_1_pkg::fourth_enum regfile_1__reg_d__f1_in,
|
||||
input [1:0] regfile_1__reg_d__f2_in,
|
||||
input enums_pkg::first_enum reg_a__f1_in ,
|
||||
input [1:0] reg_a__f2_in ,
|
||||
input enums_pkg::second_enum reg_b__f1_in ,
|
||||
input [1:0] reg_b__f2_in ,
|
||||
|
||||
// Outputs
|
||||
output HREADYOUT ,
|
||||
output HREADYOUT,
|
||||
output HRESP ,
|
||||
output [32-1:0] HRDATA ,
|
||||
output enums_pkg::third_enum regfile_1__reg_c__f1_r,
|
||||
output [1:0] regfile_1__reg_c__f2_r,
|
||||
output enums__regfile_1_pkg::fourth_enum regfile_1__reg_d__f1_r,
|
||||
output [1:0] regfile_1__reg_d__f2_r,
|
||||
|
||||
// Ports for 'regfile_1__reg_c'
|
||||
input enums_pkg::third_enum regfile_1__reg_c__f1_in,
|
||||
output enums_pkg::third_enum regfile_1__reg_c__f1_r ,
|
||||
input [1:0] regfile_1__reg_c__f2_in,
|
||||
output [1:0] regfile_1__reg_c__f2_r ,
|
||||
|
||||
// Ports for 'regfile_1__reg_d'
|
||||
input enums__regfile_1_pkg::fourth_enum regfile_1__reg_d__f1_in,
|
||||
output enums__regfile_1_pkg::fourth_enum regfile_1__reg_d__f1_r ,
|
||||
input [1:0] regfile_1__reg_d__f2_in,
|
||||
output [1:0] regfile_1__reg_d__f2_r ,
|
||||
|
||||
// Ports for 'reg_a'
|
||||
input enums_pkg::first_enum reg_a__f1_in,
|
||||
output enums_pkg::first_enum reg_a__f1_r ,
|
||||
input [1:0] reg_a__f2_in,
|
||||
output [1:0] reg_a__f2_r ,
|
||||
|
||||
// Ports for 'reg_b'
|
||||
input enums_pkg::second_enum reg_b__f1_in,
|
||||
output enums_pkg::second_enum reg_b__f1_r ,
|
||||
input [1:0] reg_b__f2_in,
|
||||
output [1:0] reg_b__f2_r
|
||||
|
||||
);
|
||||
|
||||
|
||||
@ -227,9 +237,9 @@ assign regfile_1__reg_c__f2_r = regfile_1__reg_c__f2_q;
|
||||
|
||||
|
||||
|
||||
/**************************************
|
||||
/**********************************************
|
||||
* Assign all fields to signal to Mux *
|
||||
**************************************/
|
||||
**********************************************/
|
||||
// Assign all fields. Fields that are not readable are tied to 0.
|
||||
assign regfile_1__reg_c_data_mux_in = {{22{1'b0}}, regfile_1__reg_c__f2_q, {6{1'b0}}, regfile_1__reg_c__f1_q};
|
||||
|
||||
@ -317,9 +327,9 @@ assign regfile_1__reg_d__f2_r = regfile_1__reg_d__f2_q;
|
||||
|
||||
|
||||
|
||||
/**************************************
|
||||
/**********************************************
|
||||
* Assign all fields to signal to Mux *
|
||||
**************************************/
|
||||
**********************************************/
|
||||
// Assign all fields. Fields that are not readable are tied to 0.
|
||||
assign regfile_1__reg_d_data_mux_in = {{22{1'b0}}, regfile_1__reg_d__f2_q, {6{1'b0}}, regfile_1__reg_d__f1_q};
|
||||
|
||||
@ -407,9 +417,9 @@ assign reg_a__f2_r = reg_a__f2_q;
|
||||
|
||||
|
||||
|
||||
/**************************************
|
||||
/**********************************************
|
||||
* Assign all fields to signal to Mux *
|
||||
**************************************/
|
||||
**********************************************/
|
||||
// Assign all fields. Fields that are not readable are tied to 0.
|
||||
assign reg_a_data_mux_in = {{22{1'b0}}, reg_a__f2_q, {6{1'b0}}, reg_a__f1_q};
|
||||
|
||||
@ -497,9 +507,9 @@ assign reg_b__f2_r = reg_b__f2_q;
|
||||
|
||||
|
||||
|
||||
/**************************************
|
||||
/**********************************************
|
||||
* Assign all fields to signal to Mux *
|
||||
**************************************/
|
||||
**********************************************/
|
||||
// Assign all fields. Fields that are not readable are tied to 0.
|
||||
assign reg_b_data_mux_in = {{22{1'b0}}, reg_b__f2_q, {6{1'b0}}, reg_b__f1_q};
|
||||
|
||||
|
||||
@ -20,7 +20,7 @@
|
||||
*
|
||||
* Generation information:
|
||||
* - User: : dpotter
|
||||
* - Time : November 02 2021 23:27:37
|
||||
* - Time : November 26 2021 16:32:57
|
||||
* - Path : /home/dpotter/srdl2sv/examples/hierarchical_regfiles
|
||||
* - RDL file : ['hierarchical_regfiles.rdl']
|
||||
* - Hostname : ArchXPS
|
||||
@ -35,6 +35,7 @@
|
||||
* - Use Real Tabs : False
|
||||
* - Tab Width : 4
|
||||
* - Enums Enabled : True
|
||||
* - Address Errors : True
|
||||
* - Unpacked I/Os : True
|
||||
* - Register Bus Type: amba3ahblite
|
||||
* - Address width : 32
|
||||
@ -69,11 +70,13 @@
|
||||
module hierarchical_regfiles
|
||||
|
||||
(
|
||||
// Resets
|
||||
// Reset signals declared for registers
|
||||
|
||||
|
||||
// Inputs
|
||||
input clk ,
|
||||
// Ports for 'General Clock'
|
||||
input clk,
|
||||
|
||||
// Ports for 'AHB Protocol'
|
||||
input HRESETn ,
|
||||
input [31:0] HADDR ,
|
||||
input HWRITE ,
|
||||
@ -82,36 +85,45 @@ module hierarchical_regfiles
|
||||
input [1:0] HTRANS ,
|
||||
input [32-1:0] HWDATA ,
|
||||
input HSEL ,
|
||||
input regfile_1__reg_a__f1_hw_wr ,
|
||||
input [15:0] regfile_1__reg_a__f1_in ,
|
||||
input regfile_1__reg_a__f2_hw_wr ,
|
||||
input [15:0] regfile_1__reg_a__f2_in ,
|
||||
input regfile_1__reg_b__f1_hw_wr ,
|
||||
input [15:0] regfile_1__reg_b__f1_in ,
|
||||
input regfile_1__reg_b__f2_hw_wr ,
|
||||
input [15:0] regfile_1__reg_b__f2_in ,
|
||||
input [15:0] regfile_2__regfile_3__reg_d__f1_in[3][4][2],
|
||||
input [15:0] regfile_2__regfile_3__reg_d__f2_in[3][4][2],
|
||||
input [7:0] regfile_2__reg_c__f1_in [3],
|
||||
input [15:0] regfile_2__reg_c__f3_in [3],
|
||||
input reg_e__f1_hw_wr ,
|
||||
input [15:0] reg_e__f1_in ,
|
||||
input reg_e__f2_hw_wr ,
|
||||
input [15:0] reg_e__f2_in ,
|
||||
|
||||
// Outputs
|
||||
output HREADYOUT ,
|
||||
output HREADYOUT,
|
||||
output HRESP ,
|
||||
output [32-1:0] HRDATA ,
|
||||
|
||||
// Ports for 'regfile_1__reg_a'
|
||||
input regfile_1__reg_a__f1_hw_wr,
|
||||
input [15:0] regfile_1__reg_a__f1_in ,
|
||||
output [15:0] regfile_1__reg_a__f1_r ,
|
||||
input regfile_1__reg_a__f2_hw_wr,
|
||||
input [15:0] regfile_1__reg_a__f2_in ,
|
||||
output [15:0] regfile_1__reg_a__f2_r ,
|
||||
|
||||
// Ports for 'regfile_1__reg_b'
|
||||
input regfile_1__reg_b__f1_hw_wr,
|
||||
input [15:0] regfile_1__reg_b__f1_in ,
|
||||
output [15:0] regfile_1__reg_b__f1_r ,
|
||||
input regfile_1__reg_b__f2_hw_wr,
|
||||
input [15:0] regfile_1__reg_b__f2_in ,
|
||||
output [15:0] regfile_1__reg_b__f2_r ,
|
||||
output [15:0] regfile_2__regfile_3__reg_d__f1_r[3][4][2],
|
||||
output [15:0] regfile_2__regfile_3__reg_d__f2_r[3][4][2],
|
||||
|
||||
// Ports for 'regfile_2__regfile_3__reg_d'
|
||||
input [15:0] regfile_2__regfile_3__reg_d__f1_in[3][4][2],
|
||||
output [15:0] regfile_2__regfile_3__reg_d__f1_r [3][4][2],
|
||||
input [15:0] regfile_2__regfile_3__reg_d__f2_in[3][4][2],
|
||||
output [15:0] regfile_2__regfile_3__reg_d__f2_r [3][4][2],
|
||||
|
||||
// Ports for 'regfile_2__reg_c'
|
||||
input [7:0] regfile_2__reg_c__f1_in[3],
|
||||
output [7:0] regfile_2__reg_c__f2_r [3],
|
||||
input [15:0] regfile_2__reg_c__f3_in[3],
|
||||
|
||||
// Ports for 'reg_e'
|
||||
input reg_e__f1_hw_wr,
|
||||
input [15:0] reg_e__f1_in ,
|
||||
output [15:0] reg_e__f1_r ,
|
||||
input reg_e__f2_hw_wr,
|
||||
input [15:0] reg_e__f2_in ,
|
||||
output [15:0] reg_e__f2_r
|
||||
|
||||
);
|
||||
|
||||
|
||||
@ -242,9 +254,9 @@ assign regfile_1__reg_a__f2_r = regfile_1__reg_a__f2_q;
|
||||
|
||||
|
||||
|
||||
/**************************************
|
||||
/**********************************************
|
||||
* Assign all fields to signal to Mux *
|
||||
**************************************/
|
||||
**********************************************/
|
||||
// Assign all fields. Fields that are not readable are tied to 0.
|
||||
assign regfile_1__reg_a_data_mux_in = {regfile_1__reg_a__f2_q, regfile_1__reg_a__f1_q};
|
||||
|
||||
@ -336,9 +348,9 @@ assign regfile_1__reg_b__f2_r = regfile_1__reg_b__f2_q;
|
||||
|
||||
|
||||
|
||||
/**************************************
|
||||
/**********************************************
|
||||
* Assign all fields to signal to Mux *
|
||||
**************************************/
|
||||
**********************************************/
|
||||
// Assign all fields. Fields that are not readable are tied to 0.
|
||||
assign regfile_1__reg_b_data_mux_in = {regfile_1__reg_b__f2_q, regfile_1__reg_b__f1_q};
|
||||
|
||||
@ -465,9 +477,9 @@ begin
|
||||
|
||||
|
||||
|
||||
/**************************************
|
||||
/**********************************************
|
||||
* Assign all fields to signal to Mux *
|
||||
**************************************/
|
||||
**********************************************/
|
||||
// Assign all fields. Fields that are not readable are tied to 0.
|
||||
assign regfile_2__regfile_3__reg_d_data_mux_in[gv_a][gv_b][gv_c] = {regfile_2__regfile_3__reg_d__f2_q[gv_a][gv_b][gv_c], regfile_2__regfile_3__reg_d__f1_q[gv_a][gv_b][gv_c]};
|
||||
|
||||
@ -509,6 +521,8 @@ begin
|
||||
// a reset, or change the sw/hw access properties
|
||||
assign regfile_2__reg_c__f1_q[gv_a] = regfile_2__reg_c__f1_in[gv_a];
|
||||
|
||||
|
||||
|
||||
//-----------------FIELD SUMMARY-----------------
|
||||
// name : f2 (regfile_2__reg_c[15:8])
|
||||
// access : hw = r
|
||||
@ -525,6 +539,8 @@ begin
|
||||
// Connect register to hardware output port
|
||||
assign regfile_2__reg_c__f2_r[gv_a] = regfile_2__reg_c__f2_q[gv_a];
|
||||
|
||||
|
||||
|
||||
//-----------------FIELD SUMMARY-----------------
|
||||
// name : f3 (regfile_2__reg_c[31:16])
|
||||
// access : hw = w
|
||||
@ -552,9 +568,9 @@ begin
|
||||
|
||||
|
||||
|
||||
/**************************************
|
||||
/**********************************************
|
||||
* Assign all fields to signal to Mux *
|
||||
**************************************/
|
||||
**********************************************/
|
||||
// Assign all fields. Fields that are not readable are tied to 0.
|
||||
assign regfile_2__reg_c_data_mux_in[gv_a] = {regfile_2__reg_c__f3_q[gv_a], regfile_2__reg_c__f2_q[gv_a], regfile_2__reg_c__f1_q[gv_a]};
|
||||
|
||||
@ -649,9 +665,9 @@ assign reg_e__f2_r = reg_e__f2_q;
|
||||
|
||||
|
||||
|
||||
/**************************************
|
||||
/**********************************************
|
||||
* Assign all fields to signal to Mux *
|
||||
**************************************/
|
||||
**********************************************/
|
||||
// Assign all fields. Fields that are not readable are tied to 0.
|
||||
assign reg_e_data_mux_in = {reg_e__f2_q, reg_e__f1_q};
|
||||
|
||||
|
||||
@ -20,7 +20,7 @@
|
||||
*
|
||||
* Generation information:
|
||||
* - User: : dpotter
|
||||
* - Time : November 02 2021 23:27:21
|
||||
* - Time : November 26 2021 16:32:57
|
||||
* - Path : /home/dpotter/srdl2sv/examples/interrupt_hierarchy
|
||||
* - RDL file : ['interrupt_hierarchy.rdl']
|
||||
* - Hostname : ArchXPS
|
||||
@ -35,6 +35,7 @@
|
||||
* - Use Real Tabs : False
|
||||
* - Tab Width : 4
|
||||
* - Enums Enabled : True
|
||||
* - Address Errors : True
|
||||
* - Unpacked I/Os : True
|
||||
* - Register Bus Type: amba3ahblite
|
||||
* - Address width : 32
|
||||
@ -69,11 +70,13 @@
|
||||
module interrupt_hierarchy
|
||||
|
||||
(
|
||||
// Resets
|
||||
// Reset signals declared for registers
|
||||
input field_reset_n,
|
||||
|
||||
// Inputs
|
||||
input clk ,
|
||||
// Ports for 'General Clock'
|
||||
input clk,
|
||||
|
||||
// Ports for 'AHB Protocol'
|
||||
input HRESETn ,
|
||||
input [31:0] HADDR ,
|
||||
input HWRITE ,
|
||||
@ -82,40 +85,53 @@ module interrupt_hierarchy
|
||||
input [1:0] HTRANS ,
|
||||
input [32-1:0] HWDATA ,
|
||||
input HSEL ,
|
||||
output HREADYOUT,
|
||||
output HRESP ,
|
||||
output [32-1:0] HRDATA ,
|
||||
|
||||
// Ports for 'block_a_int'
|
||||
output block_a_int_intr ,
|
||||
output block_a_int_halt ,
|
||||
input [0:0] block_a_int__crc_error_in ,
|
||||
input [0:0] block_a_int__len_error_in ,
|
||||
input [0:0] block_a_int__multi_bit_ecc_error_in,
|
||||
input [3:0] block_a_int__active_ecc_master_in ,
|
||||
|
||||
// Ports for 'block_b_int'
|
||||
output block_b_int_intr ,
|
||||
output block_b_int_halt ,
|
||||
input [0:0] block_b_int__crc_error_in ,
|
||||
input [0:0] block_b_int__len_error_in ,
|
||||
input [0:0] block_b_int__multi_bit_ecc_error_in,
|
||||
input [3:0] block_b_int__active_ecc_master_in ,
|
||||
|
||||
// Ports for 'block_c_int'
|
||||
output block_c_int_intr ,
|
||||
output block_c_int_halt ,
|
||||
input [0:0] block_c_int__crc_error_in ,
|
||||
input [0:0] block_c_int__len_error_in ,
|
||||
input [0:0] block_c_int__multi_bit_ecc_error_in,
|
||||
input [3:0] block_c_int__active_ecc_master_in ,
|
||||
|
||||
// Ports for 'block_d_int'
|
||||
output block_d_int_intr ,
|
||||
output block_d_int_halt ,
|
||||
input [0:0] block_d_int__crc_error_in ,
|
||||
input [0:0] block_d_int__len_error_in ,
|
||||
input [0:0] block_d_int__multi_bit_ecc_error_in,
|
||||
input [3:0] block_d_int__active_ecc_master_in ,
|
||||
|
||||
// Outputs
|
||||
output HREADYOUT ,
|
||||
output HRESP ,
|
||||
output [32-1:0] HRDATA ,
|
||||
output block_a_int_intr,
|
||||
output block_a_int_halt,
|
||||
output block_b_int_intr,
|
||||
output block_b_int_halt,
|
||||
output block_c_int_intr,
|
||||
output block_c_int_halt,
|
||||
output block_d_int_intr,
|
||||
output block_d_int_halt,
|
||||
output master_int_intr ,
|
||||
// Ports for 'master_int'
|
||||
output master_int_intr,
|
||||
|
||||
// Ports for 'master_halt'
|
||||
output master_halt_intr,
|
||||
output master_halt_halt,
|
||||
output global_int_intr ,
|
||||
|
||||
// Ports for 'global_int'
|
||||
output global_int_intr,
|
||||
output global_int_halt
|
||||
|
||||
);
|
||||
|
||||
|
||||
@ -175,7 +191,7 @@ logic [0:0] block_a_int__len_error_sticky_latch ;
|
||||
logic [0:0] block_a_int__multi_bit_ecc_error_q ;
|
||||
logic [0:0] block_a_int__multi_bit_ecc_error_sticky_latch;
|
||||
logic [3:0] block_a_int__active_ecc_master_q ;
|
||||
logic [3:0] block_a_int__active_ecc_master_sticky_latch;
|
||||
logic [3:0] block_a_int__active_ecc_master_sticky_latch ;
|
||||
|
||||
|
||||
// Register-activation for 'block_a_int'
|
||||
@ -346,9 +362,9 @@ assign block_a_int_intr = |(block_a_int__crc_error_q & block_a_int_en__crc_error
|
||||
assign block_a_int_halt = |(block_a_int__crc_error_q & ~block_a_halt_en__crc_error_q) || |(block_a_int__len_error_q & ~block_a_halt_en__len_error_q) || |(block_a_int__multi_bit_ecc_error_q & ~block_a_halt_en__multi_bit_ecc_error_q);
|
||||
|
||||
|
||||
/**************************************
|
||||
/**********************************************
|
||||
* Assign all fields to signal to Mux *
|
||||
**************************************/
|
||||
**********************************************/
|
||||
// Assign all fields. Fields that are not readable are tied to 0.
|
||||
assign block_a_int_data_mux_in = {{24{1'b0}}, block_a_int__active_ecc_master_q, {1{1'b0}}, block_a_int__multi_bit_ecc_error_q, block_a_int__len_error_q, block_a_int__crc_error_q};
|
||||
|
||||
@ -461,9 +477,9 @@ end // of block_a_int_en__multi_bit_ecc_error's always_ff
|
||||
|
||||
|
||||
|
||||
/**************************************
|
||||
/**********************************************
|
||||
* Assign all fields to signal to Mux *
|
||||
**************************************/
|
||||
**********************************************/
|
||||
// Assign all fields. Fields that are not readable are tied to 0.
|
||||
assign block_a_int_en_data_mux_in = {{29{1'b0}}, block_a_int_en__multi_bit_ecc_error_q, block_a_int_en__len_error_q, block_a_int_en__crc_error_q};
|
||||
|
||||
@ -576,9 +592,9 @@ end // of block_a_halt_en__multi_bit_ecc_error's always_ff
|
||||
|
||||
|
||||
|
||||
/**************************************
|
||||
/**********************************************
|
||||
* Assign all fields to signal to Mux *
|
||||
**************************************/
|
||||
**********************************************/
|
||||
// Assign all fields. Fields that are not readable are tied to 0.
|
||||
assign block_a_halt_en_data_mux_in = {{29{1'b0}}, block_a_halt_en__multi_bit_ecc_error_q, block_a_halt_en__len_error_q, block_a_halt_en__crc_error_q};
|
||||
|
||||
@ -610,7 +626,7 @@ logic [0:0] block_b_int__len_error_sticky_latch ;
|
||||
logic [0:0] block_b_int__multi_bit_ecc_error_q ;
|
||||
logic [0:0] block_b_int__multi_bit_ecc_error_sticky_latch;
|
||||
logic [3:0] block_b_int__active_ecc_master_q ;
|
||||
logic [3:0] block_b_int__active_ecc_master_sticky_latch;
|
||||
logic [3:0] block_b_int__active_ecc_master_sticky_latch ;
|
||||
|
||||
|
||||
// Register-activation for 'block_b_int'
|
||||
@ -781,9 +797,9 @@ assign block_b_int_intr = |(block_b_int__crc_error_q & block_b_int_en__crc_error
|
||||
assign block_b_int_halt = |(block_b_int__crc_error_q & ~block_b_halt_en__crc_error_q) || |(block_b_int__len_error_q & ~block_b_halt_en__len_error_q) || |(block_b_int__multi_bit_ecc_error_q & ~block_b_halt_en__multi_bit_ecc_error_q);
|
||||
|
||||
|
||||
/**************************************
|
||||
/**********************************************
|
||||
* Assign all fields to signal to Mux *
|
||||
**************************************/
|
||||
**********************************************/
|
||||
// Assign all fields. Fields that are not readable are tied to 0.
|
||||
assign block_b_int_data_mux_in = {{24{1'b0}}, block_b_int__active_ecc_master_q, {1{1'b0}}, block_b_int__multi_bit_ecc_error_q, block_b_int__len_error_q, block_b_int__crc_error_q};
|
||||
|
||||
@ -896,9 +912,9 @@ end // of block_b_int_en__multi_bit_ecc_error's always_ff
|
||||
|
||||
|
||||
|
||||
/**************************************
|
||||
/**********************************************
|
||||
* Assign all fields to signal to Mux *
|
||||
**************************************/
|
||||
**********************************************/
|
||||
// Assign all fields. Fields that are not readable are tied to 0.
|
||||
assign block_b_int_en_data_mux_in = {{29{1'b0}}, block_b_int_en__multi_bit_ecc_error_q, block_b_int_en__len_error_q, block_b_int_en__crc_error_q};
|
||||
|
||||
@ -1011,9 +1027,9 @@ end // of block_b_halt_en__multi_bit_ecc_error's always_ff
|
||||
|
||||
|
||||
|
||||
/**************************************
|
||||
/**********************************************
|
||||
* Assign all fields to signal to Mux *
|
||||
**************************************/
|
||||
**********************************************/
|
||||
// Assign all fields. Fields that are not readable are tied to 0.
|
||||
assign block_b_halt_en_data_mux_in = {{29{1'b0}}, block_b_halt_en__multi_bit_ecc_error_q, block_b_halt_en__len_error_q, block_b_halt_en__crc_error_q};
|
||||
|
||||
@ -1045,7 +1061,7 @@ logic [0:0] block_c_int__len_error_sticky_latch ;
|
||||
logic [0:0] block_c_int__multi_bit_ecc_error_q ;
|
||||
logic [0:0] block_c_int__multi_bit_ecc_error_sticky_latch;
|
||||
logic [3:0] block_c_int__active_ecc_master_q ;
|
||||
logic [3:0] block_c_int__active_ecc_master_sticky_latch;
|
||||
logic [3:0] block_c_int__active_ecc_master_sticky_latch ;
|
||||
|
||||
|
||||
// Register-activation for 'block_c_int'
|
||||
@ -1216,9 +1232,9 @@ assign block_c_int_intr = |(block_c_int__crc_error_q & block_c_int_en__crc_error
|
||||
assign block_c_int_halt = |(block_c_int__crc_error_q & ~block_c_halt_en__crc_error_q) || |(block_c_int__len_error_q & ~block_c_halt_en__len_error_q) || |(block_c_int__multi_bit_ecc_error_q & ~block_c_halt_en__multi_bit_ecc_error_q);
|
||||
|
||||
|
||||
/**************************************
|
||||
/**********************************************
|
||||
* Assign all fields to signal to Mux *
|
||||
**************************************/
|
||||
**********************************************/
|
||||
// Assign all fields. Fields that are not readable are tied to 0.
|
||||
assign block_c_int_data_mux_in = {{24{1'b0}}, block_c_int__active_ecc_master_q, {1{1'b0}}, block_c_int__multi_bit_ecc_error_q, block_c_int__len_error_q, block_c_int__crc_error_q};
|
||||
|
||||
@ -1331,9 +1347,9 @@ end // of block_c_int_en__multi_bit_ecc_error's always_ff
|
||||
|
||||
|
||||
|
||||
/**************************************
|
||||
/**********************************************
|
||||
* Assign all fields to signal to Mux *
|
||||
**************************************/
|
||||
**********************************************/
|
||||
// Assign all fields. Fields that are not readable are tied to 0.
|
||||
assign block_c_int_en_data_mux_in = {{29{1'b0}}, block_c_int_en__multi_bit_ecc_error_q, block_c_int_en__len_error_q, block_c_int_en__crc_error_q};
|
||||
|
||||
@ -1446,9 +1462,9 @@ end // of block_c_halt_en__multi_bit_ecc_error's always_ff
|
||||
|
||||
|
||||
|
||||
/**************************************
|
||||
/**********************************************
|
||||
* Assign all fields to signal to Mux *
|
||||
**************************************/
|
||||
**********************************************/
|
||||
// Assign all fields. Fields that are not readable are tied to 0.
|
||||
assign block_c_halt_en_data_mux_in = {{29{1'b0}}, block_c_halt_en__multi_bit_ecc_error_q, block_c_halt_en__len_error_q, block_c_halt_en__crc_error_q};
|
||||
|
||||
@ -1480,7 +1496,7 @@ logic [0:0] block_d_int__len_error_sticky_latch ;
|
||||
logic [0:0] block_d_int__multi_bit_ecc_error_q ;
|
||||
logic [0:0] block_d_int__multi_bit_ecc_error_sticky_latch;
|
||||
logic [3:0] block_d_int__active_ecc_master_q ;
|
||||
logic [3:0] block_d_int__active_ecc_master_sticky_latch;
|
||||
logic [3:0] block_d_int__active_ecc_master_sticky_latch ;
|
||||
|
||||
|
||||
// Register-activation for 'block_d_int'
|
||||
@ -1651,9 +1667,9 @@ assign block_d_int_intr = |(block_d_int__crc_error_q & block_d_int_en__crc_error
|
||||
assign block_d_int_halt = |(block_d_int__crc_error_q & ~block_d_halt_en__crc_error_q) || |(block_d_int__len_error_q & ~block_d_halt_en__len_error_q) || |(block_d_int__multi_bit_ecc_error_q & ~block_d_halt_en__multi_bit_ecc_error_q);
|
||||
|
||||
|
||||
/**************************************
|
||||
/**********************************************
|
||||
* Assign all fields to signal to Mux *
|
||||
**************************************/
|
||||
**********************************************/
|
||||
// Assign all fields. Fields that are not readable are tied to 0.
|
||||
assign block_d_int_data_mux_in = {{24{1'b0}}, block_d_int__active_ecc_master_q, {1{1'b0}}, block_d_int__multi_bit_ecc_error_q, block_d_int__len_error_q, block_d_int__crc_error_q};
|
||||
|
||||
@ -1766,9 +1782,9 @@ end // of block_d_int_en__multi_bit_ecc_error's always_ff
|
||||
|
||||
|
||||
|
||||
/**************************************
|
||||
/**********************************************
|
||||
* Assign all fields to signal to Mux *
|
||||
**************************************/
|
||||
**********************************************/
|
||||
// Assign all fields. Fields that are not readable are tied to 0.
|
||||
assign block_d_int_en_data_mux_in = {{29{1'b0}}, block_d_int_en__multi_bit_ecc_error_q, block_d_int_en__len_error_q, block_d_int_en__crc_error_q};
|
||||
|
||||
@ -1881,9 +1897,9 @@ end // of block_d_halt_en__multi_bit_ecc_error's always_ff
|
||||
|
||||
|
||||
|
||||
/**************************************
|
||||
/**********************************************
|
||||
* Assign all fields to signal to Mux *
|
||||
**************************************/
|
||||
**********************************************/
|
||||
// Assign all fields. Fields that are not readable are tied to 0.
|
||||
assign block_d_halt_en_data_mux_in = {{29{1'b0}}, block_d_halt_en__multi_bit_ecc_error_q, block_d_halt_en__len_error_q, block_d_halt_en__crc_error_q};
|
||||
|
||||
@ -2022,9 +2038,9 @@ end // of master_int__module_d_int's always_ff
|
||||
assign master_int_intr = |(master_int__module_a_int_q & master_int_en__module_a_int_en_q) || |(master_int__module_b_int_q & master_int_en__module_b_int_en_q) || |(master_int__module_c_int_q & master_int_en__module_c_int_en_q) || |(master_int__module_d_int_q & master_int_en__module_d_int_en_q);
|
||||
|
||||
|
||||
/**************************************
|
||||
/**********************************************
|
||||
* Assign all fields to signal to Mux *
|
||||
**************************************/
|
||||
**********************************************/
|
||||
// Assign all fields. Fields that are not readable are tied to 0.
|
||||
assign master_int_data_mux_in = {{28{1'b0}}, master_int__module_d_int_q, master_int__module_c_int_q, master_int__module_b_int_q, master_int__module_a_int_q};
|
||||
|
||||
@ -2166,9 +2182,9 @@ assign master_halt_intr = |(master_halt__module_a_int_q) || |(master_halt__modul
|
||||
assign master_halt_halt = |(master_halt__module_a_int_q & ~master_halt_en__module_a_halt_en_q) || |(master_halt__module_b_int_q & ~master_halt_en__module_b_halt_en_q) || |(master_halt__module_c_int_q & ~master_halt_en__module_c_halt_en_q) || |(master_halt__module_d_int_q & ~master_halt_en__module_d_halt_en_q);
|
||||
|
||||
|
||||
/**************************************
|
||||
/**********************************************
|
||||
* Assign all fields to signal to Mux *
|
||||
**************************************/
|
||||
**********************************************/
|
||||
// Assign all fields. Fields that are not readable are tied to 0.
|
||||
assign master_halt_data_mux_in = {{28{1'b0}}, master_halt__module_d_int_q, master_halt__module_c_int_q, master_halt__module_b_int_q, master_halt__module_a_int_q};
|
||||
|
||||
@ -2308,9 +2324,9 @@ end // of master_int_en__module_d_int_en's always_ff
|
||||
|
||||
|
||||
|
||||
/**************************************
|
||||
/**********************************************
|
||||
* Assign all fields to signal to Mux *
|
||||
**************************************/
|
||||
**********************************************/
|
||||
// Assign all fields. Fields that are not readable are tied to 0.
|
||||
assign master_int_en_data_mux_in = {{28{1'b0}}, master_int_en__module_d_int_en_q, master_int_en__module_c_int_en_q, master_int_en__module_b_int_en_q, master_int_en__module_a_int_en_q};
|
||||
|
||||
@ -2450,9 +2466,9 @@ end // of master_halt_en__module_d_halt_en's always_ff
|
||||
|
||||
|
||||
|
||||
/**************************************
|
||||
/**********************************************
|
||||
* Assign all fields to signal to Mux *
|
||||
**************************************/
|
||||
**********************************************/
|
||||
// Assign all fields. Fields that are not readable are tied to 0.
|
||||
assign master_halt_en_data_mux_in = {{28{1'b0}}, master_halt_en__module_d_halt_en_q, master_halt_en__module_c_halt_en_q, master_halt_en__module_b_halt_en_q, master_halt_en__module_a_halt_en_q};
|
||||
|
||||
@ -2542,9 +2558,9 @@ assign global_int_intr = |(global_int__global_int_q & global_int_en__global_int_
|
||||
assign global_int_halt = |(global_int__global_int_q) || |(global_int__global_halt_q & ~global_int_en__global_halt_en_q);
|
||||
|
||||
|
||||
/**************************************
|
||||
/**********************************************
|
||||
* Assign all fields to signal to Mux *
|
||||
**************************************/
|
||||
**********************************************/
|
||||
// Assign all fields. Fields that are not readable are tied to 0.
|
||||
assign global_int_data_mux_in = {{30{1'b0}}, global_int__global_halt_q, global_int__global_int_q};
|
||||
|
||||
@ -2630,9 +2646,9 @@ end // of global_int_en__global_halt_en's always_ff
|
||||
|
||||
|
||||
|
||||
/**************************************
|
||||
/**********************************************
|
||||
* Assign all fields to signal to Mux *
|
||||
**************************************/
|
||||
**********************************************/
|
||||
// Assign all fields. Fields that are not readable are tied to 0.
|
||||
assign global_int_en_data_mux_in = {{30{1'b0}}, global_int_en__global_halt_en_q, global_int_en__global_int_en_q};
|
||||
|
||||
|
||||
@ -20,7 +20,7 @@
|
||||
*
|
||||
* Generation information:
|
||||
* - User: : dpotter
|
||||
* - Time : November 04 2021 23:31:13
|
||||
* - Time : November 26 2021 16:33:16
|
||||
* - Path : /home/dpotter/srdl2sv/examples/parameters
|
||||
* - RDL file : ['parameters.rdl']
|
||||
* - Hostname : ArchXPS
|
||||
@ -35,6 +35,7 @@
|
||||
* - Use Real Tabs : False
|
||||
* - Tab Width : 4
|
||||
* - Enums Enabled : True
|
||||
* - Address Errors : True
|
||||
* - Unpacked I/Os : True
|
||||
* - Register Bus Type: amba3ahblite
|
||||
* - Address width : 32
|
||||
@ -69,11 +70,13 @@
|
||||
module paremeters
|
||||
|
||||
(
|
||||
// Resets
|
||||
// Reset signals declared for registers
|
||||
input rst_async_n,
|
||||
|
||||
// Inputs
|
||||
input clk ,
|
||||
// Ports for 'General Clock'
|
||||
input clk,
|
||||
|
||||
// Ports for 'AHB Protocol'
|
||||
input HRESETn ,
|
||||
input [31:0] HADDR ,
|
||||
input HWRITE ,
|
||||
@ -82,19 +85,26 @@ module paremeters
|
||||
input [1:0] HTRANS ,
|
||||
input [32-1:0] HWDATA ,
|
||||
input HSEL ,
|
||||
input [31:0] reg32__data_in ,
|
||||
input [31:0] reg32_arr__data_in[8],
|
||||
input [15:0] reg16__data_in ,
|
||||
input [7:0] reg8__data_in ,
|
||||
|
||||
// Outputs
|
||||
output HREADYOUT ,
|
||||
output HREADYOUT,
|
||||
output HRESP ,
|
||||
output [32-1:0] HRDATA ,
|
||||
|
||||
// Ports for 'reg32'
|
||||
input [31:0] reg32__data_in,
|
||||
output [31:0] reg32__data_r ,
|
||||
output [31:0] reg32_arr__data_r[8],
|
||||
|
||||
// Ports for 'reg32_arr'
|
||||
input [31:0] reg32_arr__data_in[8],
|
||||
output [31:0] reg32_arr__data_r [8],
|
||||
|
||||
// Ports for 'reg16'
|
||||
input [15:0] reg16__data_in,
|
||||
output [15:0] reg16__data_r ,
|
||||
|
||||
// Ports for 'reg8'
|
||||
input [7:0] reg8__data_in,
|
||||
output [7:0] reg8__data_r
|
||||
|
||||
);
|
||||
|
||||
|
||||
@ -196,9 +206,9 @@ assign reg32__data_r = reg32__data_q;
|
||||
|
||||
|
||||
|
||||
/**************************************
|
||||
/**********************************************
|
||||
* Assign all fields to signal to Mux *
|
||||
**************************************/
|
||||
**********************************************/
|
||||
// Assign all fields. Fields that are not readable are tied to 0.
|
||||
assign reg32_data_mux_in = {reg32__data_q};
|
||||
|
||||
@ -272,9 +282,9 @@ begin
|
||||
|
||||
|
||||
|
||||
/**************************************
|
||||
/**********************************************
|
||||
* Assign all fields to signal to Mux *
|
||||
**************************************/
|
||||
**********************************************/
|
||||
// Assign all fields. Fields that are not readable are tied to 0.
|
||||
assign reg32_arr_data_mux_in[gv_a] = {reg32_arr__data_q[gv_a]};
|
||||
|
||||
@ -300,7 +310,7 @@ endgenerate
|
||||
|
||||
logic reg16_active ;
|
||||
logic reg16_sw_wr ;
|
||||
logic [15:0] reg16_data_mux_in;
|
||||
logic [31:0] reg16_data_mux_in;
|
||||
logic reg16_rdy_mux_in ;
|
||||
logic reg16_err_mux_in ;
|
||||
logic [15:0] reg16__data_q ;
|
||||
@ -345,11 +355,11 @@ assign reg16__data_r = reg16__data_q;
|
||||
|
||||
|
||||
|
||||
/**************************************
|
||||
/**********************************************
|
||||
* Assign all fields to signal to Mux *
|
||||
**************************************/
|
||||
**********************************************/
|
||||
// Assign all fields. Fields that are not readable are tied to 0.
|
||||
assign reg16_data_mux_in = {reg16__data_q};
|
||||
assign reg16_data_mux_in = {{16{1'b0}}, reg16__data_q};
|
||||
|
||||
// Internal registers are ready immediately
|
||||
assign reg16_rdy_mux_in = 1'b1;
|
||||
@ -368,14 +378,14 @@ assign reg16_err_mux_in = !((widget_if.r_vld && (|widget_if.byte_en[1:0])) || (w
|
||||
/*******************************************************************/
|
||||
|
||||
logic reg8_active ;
|
||||
logic [7:0] reg8_data_mux_in;
|
||||
logic [31:0] reg8_data_mux_in;
|
||||
logic reg8_rdy_mux_in ;
|
||||
logic reg8_err_mux_in ;
|
||||
logic [7:0] reg8__data_q ;
|
||||
|
||||
|
||||
// Register-activation for 'reg8'
|
||||
assign reg8_active = widget_if.addr == 38;
|
||||
assign reg8_active = widget_if.addr == 40;
|
||||
|
||||
//-----------------FIELD SUMMARY-----------------
|
||||
// name : data (reg8[7:0])
|
||||
@ -404,11 +414,11 @@ assign reg8__data_r = reg8__data_q;
|
||||
|
||||
|
||||
|
||||
/**************************************
|
||||
/**********************************************
|
||||
* Assign all fields to signal to Mux *
|
||||
**************************************/
|
||||
**********************************************/
|
||||
// Assign all fields. Fields that are not readable are tied to 0.
|
||||
assign reg8_data_mux_in = {reg8__data_q};
|
||||
assign reg8_data_mux_in = {{24{1'b0}}, reg8__data_q};
|
||||
|
||||
// Internal registers are ready immediately
|
||||
assign reg8_rdy_mux_in = 1'b1;
|
||||
|
||||
@ -20,7 +20,7 @@
|
||||
*
|
||||
* Generation information:
|
||||
* - User: : dpotter
|
||||
* - Time : November 02 2021 23:27:37
|
||||
* - Time : November 26 2021 16:32:58
|
||||
* - Path : /home/dpotter/srdl2sv/examples/simple_rw_reg
|
||||
* - RDL file : ['simple_rw_reg.rdl']
|
||||
* - Hostname : ArchXPS
|
||||
@ -35,6 +35,7 @@
|
||||
* - Use Real Tabs : False
|
||||
* - Tab Width : 4
|
||||
* - Enums Enabled : True
|
||||
* - Address Errors : True
|
||||
* - Unpacked I/Os : True
|
||||
* - Register Bus Type: amba3ahblite
|
||||
* - Address width : 32
|
||||
@ -69,11 +70,13 @@
|
||||
module simple_rw_reg
|
||||
|
||||
(
|
||||
// Resets
|
||||
// Reset signals declared for registers
|
||||
|
||||
|
||||
// Inputs
|
||||
input clk ,
|
||||
// Ports for 'General Clock'
|
||||
input clk,
|
||||
|
||||
// Ports for 'AHB Protocol'
|
||||
input HRESETn ,
|
||||
input [31:0] HADDR ,
|
||||
input HWRITE ,
|
||||
@ -82,29 +85,34 @@ module simple_rw_reg
|
||||
input [1:0] HTRANS ,
|
||||
input [32-1:0] HWDATA ,
|
||||
input HSEL ,
|
||||
input register_1d__f1_hw_wr,
|
||||
input [15:0] register_1d__f1_in ,
|
||||
input register_1d__f2_hw_wr,
|
||||
input [15:0] register_1d__f2_in ,
|
||||
input register_2d__f1_hw_wr[2],
|
||||
input [15:0] register_2d__f1_in [2],
|
||||
input register_2d__f2_hw_wr[2],
|
||||
input [15:0] register_2d__f2_in [2],
|
||||
input register_3d__f1_hw_wr[2][2],
|
||||
input [15:0] register_3d__f1_in [2][2],
|
||||
input register_3d__f2_hw_wr[2][2],
|
||||
input [15:0] register_3d__f2_in [2][2],
|
||||
|
||||
// Outputs
|
||||
output HREADYOUT ,
|
||||
output HREADYOUT,
|
||||
output HRESP ,
|
||||
output [32-1:0] HRDATA ,
|
||||
output [15:0] register_1d__f1_r,
|
||||
output [15:0] register_1d__f2_r,
|
||||
output [15:0] register_2d__f1_r[2],
|
||||
output [15:0] register_2d__f2_r[2],
|
||||
output [15:0] register_3d__f1_r[2][2],
|
||||
output [15:0] register_3d__f2_r[2][2]
|
||||
|
||||
// Ports for 'register_1d'
|
||||
input register_1d__f1_hw_wr,
|
||||
input [15:0] register_1d__f1_in ,
|
||||
output [15:0] register_1d__f1_r ,
|
||||
input register_1d__f2_hw_wr,
|
||||
input [15:0] register_1d__f2_in ,
|
||||
output [15:0] register_1d__f2_r ,
|
||||
|
||||
// Ports for 'register_2d'
|
||||
input register_2d__f1_hw_wr[2],
|
||||
input [15:0] register_2d__f1_in [2],
|
||||
output [15:0] register_2d__f1_r [2],
|
||||
input register_2d__f2_hw_wr[2],
|
||||
input [15:0] register_2d__f2_in [2],
|
||||
output [15:0] register_2d__f2_r [2],
|
||||
|
||||
// Ports for 'register_3d'
|
||||
input register_3d__f1_hw_wr[2][2],
|
||||
input [15:0] register_3d__f1_in [2][2],
|
||||
output [15:0] register_3d__f1_r [2][2],
|
||||
input register_3d__f2_hw_wr[2][2],
|
||||
input [15:0] register_3d__f2_in [2][2],
|
||||
output [15:0] register_3d__f2_r [2][2]
|
||||
|
||||
);
|
||||
|
||||
|
||||
@ -227,9 +235,9 @@ assign register_1d__f2_r = register_1d__f2_q;
|
||||
|
||||
|
||||
|
||||
/**************************************
|
||||
/**********************************************
|
||||
* Assign all fields to signal to Mux *
|
||||
**************************************/
|
||||
**********************************************/
|
||||
// Assign all fields. Fields that are not readable are tied to 0.
|
||||
assign register_1d_data_mux_in = {register_1d__f2_q, register_1d__f1_q};
|
||||
|
||||
@ -324,9 +332,9 @@ begin
|
||||
|
||||
|
||||
|
||||
/**************************************
|
||||
/**********************************************
|
||||
* Assign all fields to signal to Mux *
|
||||
**************************************/
|
||||
**********************************************/
|
||||
// Assign all fields. Fields that are not readable are tied to 0.
|
||||
assign register_2d_data_mux_in[gv_a] = {register_2d__f2_q[gv_a], register_2d__f1_q[gv_a]};
|
||||
|
||||
@ -427,9 +435,9 @@ begin
|
||||
|
||||
|
||||
|
||||
/**************************************
|
||||
/**********************************************
|
||||
* Assign all fields to signal to Mux *
|
||||
**************************************/
|
||||
**********************************************/
|
||||
// Assign all fields. Fields that are not readable are tied to 0.
|
||||
assign register_3d_data_mux_in[gv_a][gv_b] = {register_3d__f2_q[gv_a][gv_b], register_3d__f1_q[gv_a][gv_b]};
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user