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Fix bug in <REG>_sw_wr/<REG>_sw_rd for non-array registers

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In case a register isn't instantiated as an array, the stride
value the compiler returns is set to 'None'. The RTL generator
should translate it to '0' (since it doesn't matter anyway).
This commit is contained in:
Dennis Potter 2021-05-16 12:24:52 +02:00
parent a59668de87
commit 3acd7516d3
Signed by: Dennis
GPG Key ID: 186A8AD440942BAF
1 changed files with 1 additions and 3 deletions
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4
srdl2sv/components/register.py
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@ -5,7 +5,6 @@ from systemrdl import RDLCompiler, RDLCompileError, RDLWalker, RDLListener, node
from systemrdl.node import FieldNode
# Local modules
from log.log import create_logger
from components.component import Component
from components.field import Field
from . import templates
@ -73,7 +72,7 @@ class Register(Component):
addr = self.obj.absolute_address,
genvars = self.genvars_str,
genvars_sum =self.genvars_sum_str,
stride = self.obj.array_stride,
stride = self.obj.array_stride if self.obj.array_stride else '0',
depth = self.depth))
def __process_variables(self, obj: node.RootNode):
@ -117,5 +116,4 @@ class Register(Component):
genvars_sum.append(chr(97+self.dimensions-1-i))
self.genvars_sum_str = ''.join(genvars_sum)
print(self.genvars_sum_str)