Fix bug in <REG>_sw_wr/<REG>_sw_rd for non-array registers

In case a register isn't instantiated as an array, the stride
value the compiler returns is set to 'None'. The RTL generator
should translate it to '0' (since it doesn't matter anyway).

srdl2sv/components/register.py

@@ -5,7 +5,6 @@ from systemrdl import RDLCompiler, RDLCompileError, RDLWalker, RDLListener, node
 from systemrdl.node import FieldNode
 
 # Local modules
-from log.log import create_logger
 from components.component import Component
 from components.field import Field
 from . import templates
@@ -73,7 +72,7 @@ class Register(Component):
                 addr = self.obj.absolute_address,
                 genvars = self.genvars_str,
                 genvars_sum =self.genvars_sum_str,
-                stride = self.obj.array_stride,
+                stride = self.obj.array_stride if self.obj.array_stride else '0',
                 depth = self.depth))
 
     def __process_variables(self, obj: node.RootNode):
@@ -117,5 +116,4 @@ class Register(Component):
             genvars_sum.append(chr(97+self.dimensions-1-i))
 
         self.genvars_sum_str = ''.join(genvars_sum)
-        print(self.genvars_sum_str)