Dennis/srdl2sv
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A SystemRDL 2.0 to (synthesizable) SystemVerilog compiler.
13 Commits 1 Branch 0 Tags 713 KiB
Python 92.9%
SystemVerilog 5.7%
Makefile 1.4%
3acd7516d3
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Dennis 3acd7516d3
Fix bug in <REG>_sw_wr/<REG>_sw_rd for non-array registers 
In case a register isn't instantiated as an array, the stride
value the compiler returns is set to 'None'. The RTL generator
should translate it to '0' (since it doesn't matter anyway).
2021-05-16 12:24:52 +02:00
srdl2sv Fix bug in <REG>_sw_wr/<REG>_sw_rd for non-array registers 2021-05-16 12:24:52 +02:00
.gitignore Initial commit of SRDL2SV 2021-05-02 00:58:43 +02:00
LIMITATIONS.md Initial commit of SRDL2SV 2021-05-02 00:58:43 +02:00