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Fix SW write wire and improve I/O packed dimension

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This commit is contained in:
Dennis Potter 2021-05-15 17:57:50 +02:00
parent 4738cbfe6c
commit 4b9ad7ad1b
Signed by: Dennis
GPG Key ID: 186A8AD440942BAF
2 changed files with 3 additions and 3 deletions
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4
srdl2sv/components/field.py
View File

@ -93,7 +93,7 @@ class Field(Component):
if self.sw_access in (AccessType.rw, AccessType.w):
access_rtl['sw_write'].append(
Field.templ_dict['sw_access_field'].format(
path = self.path_underscored,
path_wo_field = self.path_wo_field,
genvars = self.genvars_str))
# If field spans multiple bytes, every byte shall have a seperate enable!
@ -287,7 +287,7 @@ class Field(Component):
if self.hw_access in (AccessType.rw, AccessType.r):
self.ports['output'].append(
Port("{}_r".format(self.path_underscored),
"[{}-1:0]".format(self.obj.width) if self.obj.width > 0 else "",
"[{}:0]".format(self.obj.width-1) if self.obj.width > 1 else "",
self.dimensions
))

2
srdl2sv/components/templates/fields.yaml
View File

@ -10,7 +10,7 @@ rst_field_assign: |-
end
else
sw_access_field: |-
if ({path}_sw_wr{genvars})
if ({path_wo_field}_sw_wr{genvars})
begin
sw_access_byte: |-
if (byte_enable[{i}])