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https://github.com/Silicon1602/srdl2sv.git
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Fix SW write wire and improve I/O packed dimension
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parent
4738cbfe6c
commit
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@ -93,7 +93,7 @@ class Field(Component):
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if self.sw_access in (AccessType.rw, AccessType.w):
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if self.sw_access in (AccessType.rw, AccessType.w):
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access_rtl['sw_write'].append(
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access_rtl['sw_write'].append(
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Field.templ_dict['sw_access_field'].format(
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Field.templ_dict['sw_access_field'].format(
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path = self.path_underscored,
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path_wo_field = self.path_wo_field,
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genvars = self.genvars_str))
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genvars = self.genvars_str))
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# If field spans multiple bytes, every byte shall have a seperate enable!
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# If field spans multiple bytes, every byte shall have a seperate enable!
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@ -287,7 +287,7 @@ class Field(Component):
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if self.hw_access in (AccessType.rw, AccessType.r):
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if self.hw_access in (AccessType.rw, AccessType.r):
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self.ports['output'].append(
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self.ports['output'].append(
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Port("{}_r".format(self.path_underscored),
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Port("{}_r".format(self.path_underscored),
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"[{}-1:0]".format(self.obj.width) if self.obj.width > 0 else "",
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"[{}:0]".format(self.obj.width-1) if self.obj.width > 1 else "",
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self.dimensions
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self.dimensions
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))
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))
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@ -10,7 +10,7 @@ rst_field_assign: |-
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end
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end
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else
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else
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sw_access_field: |-
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sw_access_field: |-
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if ({path}_sw_wr{genvars})
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if ({path_wo_field}_sw_wr{genvars})
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begin
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begin
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sw_access_byte: |-
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sw_access_byte: |-
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if (byte_enable[{i}])
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if (byte_enable[{i}])
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