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https://github.com/Silicon1602/srdl2sv.git
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@@ -20,7 +20,7 @@
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*
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* Generation information:
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* - User: : dpotter
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* - Time : October 31 2021 13:59:16
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* - Time : October 31 2021 16:01:37
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* - Path : /home/dpotter/srdl2sv/examples/enums
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* - RDL file : ['enums.rdl']
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* - Hostname : ArchXPS
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@@ -35,6 +35,7 @@
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* - Use Real Tabs : False
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* - Tab Width : 4
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* - Enums Enabled : True
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* - Unpacked I/Os : True
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* - Register Bus Type: amba3ahblite
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* - Address width : 32
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* - Byte enables : True
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@@ -83,26 +84,26 @@ module enums
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input [32-1:0] HWDATA ,
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input HSEL ,
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input enums_pkg::third_enum regfile_1__reg_c__f1_in,
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input logic [1:0] regfile_1__reg_c__f2_in,
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input [1:0] regfile_1__reg_c__f2_in,
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input enums__regfile_1_pkg::fourth_enum regfile_1__reg_d__f1_in,
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input logic [1:0] regfile_1__reg_d__f2_in,
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input [1:0] regfile_1__reg_d__f2_in,
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input enums_pkg::first_enum reg_a__f1_in ,
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input logic [1:0] reg_a__f2_in ,
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input [1:0] reg_a__f2_in ,
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input enums_pkg::second_enum reg_b__f1_in ,
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input logic [1:0] reg_b__f2_in ,
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input [1:0] reg_b__f2_in ,
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// Outputs
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output HREADYOUT ,
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output HRESP ,
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output [32-1:0] HRDATA ,
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output enums_pkg::third_enum regfile_1__reg_c__f1_r,
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output logic [1:0] regfile_1__reg_c__f2_r,
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output [1:0] regfile_1__reg_c__f2_r,
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output enums__regfile_1_pkg::fourth_enum regfile_1__reg_d__f1_r,
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output logic [1:0] regfile_1__reg_d__f2_r,
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output [1:0] regfile_1__reg_d__f2_r,
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output enums_pkg::first_enum reg_a__f1_r ,
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output logic [1:0] reg_a__f2_r ,
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output [1:0] reg_a__f2_r ,
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output enums_pkg::second_enum reg_b__f1_r ,
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output logic [1:0] reg_b__f2_r
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output [1:0] reg_b__f2_r
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);
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