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Flops must not update when HREADYOUT == 0, not when r2b.rdy == 0
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@ -111,7 +111,7 @@ module srdl2sv_amba3ahblite
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begin
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// When a transfer is extended it has the side-effecxt
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// of extending the address phase of the next transfer
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if (r2b.rdy)
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if (HREADYOUT)
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begin
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addr_q <= HADDR;
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operation_q <= HWRITE ? WRITE : READ;
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@ -119,7 +119,7 @@ module srdl2sv_amba3ahblite
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end
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SEQ:
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begin
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if (r2b.rdy)
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if (HREADYOUT)
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begin
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addr_q <= addr_q; // TODO
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end
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