Flops must not update when HREADYOUT == 0, not when r2b.rdy == 0

2021-09-13 21:52:35 -07:00 · 2021-09-13 21:52:35 -07:00 · 85aa2f903c
parent a27b57009b
commit 85aa2f903c
1 changed files with 2 additions and 2 deletions
--- a/srdl2sv/components/widgets/srdl2sv_amba3ahblite.sv
+++ b/srdl2sv/components/widgets/srdl2sv_amba3ahblite.sv
@ -111,7 +111,7 @@ module srdl2sv_amba3ahblite
            begin
                // When a transfer is extended it has the side-effecxt
                // of extending the address phase of the next transfer
-                if (r2b.rdy)
+                if (HREADYOUT)
                begin
                    addr_q      <= HADDR;
                    operation_q <= HWRITE ? WRITE : READ;
@ -119,7 +119,7 @@ module srdl2sv_amba3ahblite
            end
            SEQ:
            begin
-                if (r2b.rdy)
+                if (HREADYOUT)
                begin
                    addr_q <= addr_q; // TODO
                end