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Flip r_vld and w_vld in <REG>_sw_wr/<REG>_sw_rd assignment

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Dennis Potter
2021-09-15 23:47:36 -07:00
parent fea0019aa8
commit 887164dd52
1 changed files with 4 additions and 4 deletions
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8
srdl2sv/components/templates/register.yaml
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@@ -4,8 +4,8 @@ rw_wire_assign_1_dim:
// Register-activation for '{path}' {alias}
assign {path}_accss = b2r.addr == {addr};
assign {path}_sw_wr = {path}_accss && b2r.r_vld;
assign {path}_sw_rd = {path}_accss && b2r.w_vld;
assign {path}_sw_wr = {path}_accss && b2r.w_vld;
assign {path}_sw_rd = {path}_accss && b2r.r_vld;
signals:
- name: '{path}_sw_wr'
signal_type: 'logic'
@@ -18,8 +18,8 @@ rw_wire_assign_multi_dim:
// Register-activation for '{path}' {alias}
assign {path}_accss{genvars} = b2r.addr == {addr}+({genvars_sum});
assign {path}_sw_wr{genvars} = {path}_accss{genvars} && b2r.r_vld;
assign {path}_sw_rd{genvars} = {path}_accss{genvars} && b2r.w_vld;
assign {path}_sw_wr{genvars} = {path}_accss{genvars} && b2r.w_vld;
assign {path}_sw_rd{genvars} = {path}_accss{genvars} && b2r.r_vld;
signals:
- name: '{path}_sw_wr'
signal_type: 'logic'