Replace old 'reg_clk' name by more generic 'clk'

The reason is that the template will always assume that the
bus signals and the registers are synchronous. Designers should
implement possible synchronization logic outside of this block.

srdl2sv/components/templates/addrmap.yaml

@@ -67,8 +67,7 @@ module_declaration:
         <<UNINDENT>>
         (
         <<INDENT>>
-        // Clock & Resets
-        input  reg_clk,
+        // Resets
         {resets} 
 
         // Inputs

srdl2sv/components/templates/fields.yaml

@@ -1,10 +1,10 @@
 ---
 sense_list_rst:
     rtl: |-
-        always_ff @(posedge reg_clk or {rst_edge} {rst_name})
+        always_ff @(posedge clk or {rst_edge} {rst_name})
 sense_list_no_rst: 
     rtl: |-
-        always_ff @(posedge reg_clk)
+        always_ff @(posedge clk)
 rst_field_assign: 
     rtl: |-
         if ({rst_negl}{rst_name})