Add onread/onwrite properties to field class
This commit also created a seperate private method for access related RTL and for the always_ff header. Furthermore, a bug which caused the singlepulse property to always show up was resolved. Lastly, the summary method was made truely public. So, rather than writing to the RTL list, it now returns a list and the calling method/function can decide what to do with that list.
This commit is contained in:
parent
3acd7516d3
commit
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GPG Key ID:
186A8AD440942BAF
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@ -4,10 +4,9 @@ import yaml
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from systemrdl import RDLCompiler, RDLCompileError, RDLWalker, RDLListener, node
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from systemrdl.node import FieldNode
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from systemrdl.rdltypes import PrecedenceType, AccessType
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from systemrdl.rdltypes import PrecedenceType, AccessType, OnReadType, OnWriteType
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# Local modules
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from log.log import create_logger
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from components.component import Component, Port
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from . import templates
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@ -34,126 +33,11 @@ class Field(Component):
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# can be found here: https://github.com/SystemRDL/systemrdl-compiler/issues/51
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##################################################################################
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# Print a summary
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self.summary()
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# Handle always_ff
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sense_list = 'sense_list_rst' if self.rst['async'] else 'sense_list_no_rst'
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self.rtl_header.append(
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Field.templ_dict[sense_list].format(
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clk_name = "clk",
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rst_edge = self.rst['edge'],
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rst_name = self.rst['name']))
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# Add actual reset line
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if self.rst['name']:
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self.rtl_header.append(
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Field.templ_dict['rst_field_assign'].format(
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path = self.path_underscored,
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rst_name = self.rst['name'],
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rst_negl = "!" if self.rst['active'] == "active_high" else "",
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rst_value = self.rst['value'],
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genvars = self.genvars_str))
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self.rtl_header.append("begin")
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# Not all access types are required and the order might differ
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# depending on what types are defined and what precedence is
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# set. Therefore, first add all RTL into a dictionary and
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# later place it in the right order.
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#
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# The following RTL blocks are defined:
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# - hw_write --> write access for the hardware interface
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# - sw_write --> write access for the software interface
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#
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access_rtl = dict([])
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# Define hardware access (if applicable)
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access_rtl['hw_write'] = []
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if self.hw_access in (AccessType.rw, AccessType.w):
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if self.we_or_wel:
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access_rtl['hw_write'].append(
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Field.templ_dict['hw_access_we_wel'].format(
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negl = '!' if obj.get_property('wel') else '',
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path = self.path_underscored,
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genvars = self.genvars_str))
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else:
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access_rtl['hw_write'].append(
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Field.templ_dict['hw_access_no_we_wel'])
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access_rtl['hw_write'].append(
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Field.templ_dict['hw_access_field'].format(
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path = self.path_underscored,
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genvars = self.genvars_str))
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# Define software access (if applicable)
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access_rtl['sw_write'] = []
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if self.sw_access in (AccessType.rw, AccessType.w):
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access_rtl['sw_write'].append(
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Field.templ_dict['sw_access_field'].format(
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path_wo_field = self.path_wo_field,
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genvars = self.genvars_str))
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# If field spans multiple bytes, every byte shall have a seperate enable!
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for j, i in enumerate(range(self.lsbyte, self.msbyte+1)):
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access_rtl['sw_write'].append(
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Field.templ_dict['sw_access_byte'].format(
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path = self.path_underscored,
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genvars = self.genvars_str,
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i = i,
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msb_bus = str(8*(i+1)-1 if i != self.msbyte else self.obj.msb),
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bus_w = str(8 if i != self.msbyte else self.obj.width-(8*j)),
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msb_field = str(8*(j+1)-1 if i != self.msbyte else self.obj.width-1),
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field_w = str(8 if i != self.msbyte else self.obj.width-(8*j))))
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access_rtl['sw_write'].append("end")
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# Add singlepulse property
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access_rtl['singlepulse'] = [
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Field.templ_dict['singlepulse'].format(
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path = self.path_underscored,
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genvars = self.genvars_str)
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]
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# Define else
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access_rtl['else'] = ["else"]
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# Add empty string
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access_rtl[''] = ['']
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# Check if hardware has precedence (default `precedence = sw`)
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if self.precedence == 'PrecedenceType.sw':
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order_list = ['sw_write',
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'hw_write',
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'singlepulse']
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else:
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order_list = ['hw_write',
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'sw_write',
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'singlepulse']
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# Add appropriate else
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order_list_rtl = []
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for i in order_list:
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# Still a loop and not a list comprehension since this might
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# get longer in the future and thus become unreadable
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if len(access_rtl[i]) > 0:
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order_list_rtl = [*order_list_rtl, *access_rtl[i]]
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order_list_rtl.append("else")
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# Remove last pop
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order_list_rtl.pop()
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# Chain access RTL to the rest of the RTL
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self.rtl_header = [*self.rtl_header, *order_list_rtl]
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self.rtl_header.append(
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Field.templ_dict['end_field_ff'].format(
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path = self.path_underscored))
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self.rtl_header.append(self.summary())
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# Generate RTL
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self.__add_always_ff()
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self.__add_access_rtl()
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self.__add_combo()
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self.__add_ports()
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@ -217,7 +101,7 @@ class Field(Component):
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self.rst['name'] = rst_signal.inst_name
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self.rst['async'] = rst_signal.get_property("async")
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self.rst['type'] = "asynchronous" if rst['async'] else "synchronous"
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self.rst['type'] = "asynchronous" if self.rst['async'] else "synchronous"
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# Active low or active high?
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if rst_signal.get_property("activelow"):
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@ -253,7 +137,7 @@ class Field(Component):
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misc_flags.discard('reset')
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# Add comment with summary on field's properties
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self.rtl_header.append(
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return \
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Field.templ_dict['field_comment'].format(
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name = self.obj.inst_name,
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hw_access = str(self.hw_access)[11:],
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@ -265,7 +149,179 @@ class Field(Component):
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misc_flags = misc_flags if misc_flags else '-',
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lsb = self.obj.lsb,
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msb = self.obj.msb,
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path_wo_field = self.path_wo_field))
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path_wo_field = self.path_wo_field)
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def __add_always_ff(self):
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# Handle always_ff
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sense_list = 'sense_list_rst' if self.rst['async'] else 'sense_list_no_rst'
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self.rtl_header.append(
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Field.templ_dict[sense_list].format(
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clk_name = "clk",
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rst_edge = self.rst['edge'],
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rst_name = self.rst['name']))
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# Add actual reset line
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if self.rst['name']:
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self.rtl_header.append(
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Field.templ_dict['rst_field_assign'].format(
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path = self.path_underscored,
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rst_name = self.rst['name'],
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rst_negl = "!" if self.rst['active'] == "active_high" else "",
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rst_value = self.rst['value'],
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genvars = self.genvars_str))
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self.rtl_header.append("begin")
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def __add_access_rtl(self):
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# Not all access types are required and the order might differ
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# depending on what types are defined and what precedence is
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# set. Therefore, first add all RTL into a dictionary and
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# later place it in the right order.
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#
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# The following RTL blocks are defined:
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# - hw_write --> write access for the hardware interface
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# - sw_write --> write access for the software interface
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#
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access_rtl = dict([])
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# Define hardware access (if applicable)
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access_rtl['hw_write'] = []
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if self.hw_access in (AccessType.rw, AccessType.w):
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if self.we_or_wel:
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access_rtl['hw_write'].append(
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Field.templ_dict['hw_access_we_wel'].format(
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negl = '!' if self.obj.get_property('wel') else '',
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path = self.path_underscored,
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genvars = self.genvars_str))
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else:
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access_rtl['hw_write'].append(
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Field.templ_dict['hw_access_no_we_wel'])
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access_rtl['hw_write'].append(
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Field.templ_dict['hw_access_field'].format(
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path = self.path_underscored,
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genvars = self.genvars_str))
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# Define software access (if applicable)
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access_rtl['sw_write'] = []
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if self.sw_access in (AccessType.rw, AccessType.w):
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access_rtl['sw_write'].append(
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Field.templ_dict['sw_access_field'].format(
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path_wo_field = self.path_wo_field,
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genvars = self.genvars_str))
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# Check if an onwrite property is set
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onwrite = self.obj.get_property('onwrite')
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if onwrite:
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if onwrite == OnWriteType.wuser:
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self.logger.warning("The OnReadType.wuser is not yet supported!")
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elif onwrite in (OnWriteType.wclr, OnWriteType.wset):
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access_rtl['sw_write'].append(
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Field.templ_dict[str(onwrite)].format(
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path = self.path_underscored,
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genvars = self.genvars_str,
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path_wo_field = self.path_wo_field
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)
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)
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else:
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# If field spans multiple bytes, every byte shall have a seperate enable!
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for j, i in enumerate(range(self.lsbyte, self.msbyte+1)):
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access_rtl['sw_write'].append(
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Field.templ_dict[str(onwrite)].format(
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path = self.path_underscored,
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genvars = self.genvars_str,
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i = i,
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msb_bus = str(8*(i+1)-1 if i != self.msbyte else self.obj.msb),
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bus_w = str(8 if i != self.msbyte else self.obj.width-(8*j)),
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msb_field = str(8*(j+1)-1 if i != self.msbyte else self.obj.width-1),
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field_w = str(8 if i != self.msbyte else self.obj.width-(8*j))))
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else:
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# Normal write
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# If field spans multiple bytes, every byte shall have a seperate enable!
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for j, i in enumerate(range(self.lsbyte, self.msbyte+1)):
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access_rtl['sw_write'].append(
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Field.templ_dict['sw_access_byte'].format(
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path = self.path_underscored,
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genvars = self.genvars_str,
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i = i,
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msb_bus = str(8*(i+1)-1 if i != self.msbyte else self.obj.msb),
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bus_w = str(8 if i != self.msbyte else self.obj.width-(8*j)),
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msb_field = str(8*(j+1)-1 if i != self.msbyte else self.obj.width-1),
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field_w = str(8 if i != self.msbyte else self.obj.width-(8*j))))
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access_rtl['sw_write'].append("end")
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onread = self.obj.get_property('onread')
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access_rtl['sw_read'] = []
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if self.sw_access in (AccessType.rw, AccessType.r) and onread:
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if onread == OnReadType.ruser:
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self.logger.warning("The OnReadType.ruser is not yet supported!")
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else:
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access_rtl['sw_read'].append(
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Field.templ_dict[str(onread)].format(
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path = self.path_underscored,
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genvars = self.genvars_str,
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path_wo_field = self.path_wo_field
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)
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)
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# Add singlepulse property
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if self.obj.get_property('singlepulse'):
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access_rtl['singlepulse'] = [
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Field.templ_dict['singlepulse'].format(
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path = self.path_underscored,
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genvars = self.genvars_str)
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]
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else:
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access_rtl['singlepulse'] = []
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# Define else
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access_rtl['else'] = ["else"]
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# Add empty string
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access_rtl[''] = ['']
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# Check if hardware has precedence (default `precedence = sw`)
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if self.precedence == PrecedenceType.sw:
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order_list = [
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'sw_write',
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'sw_read',
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'hw_write',
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'singlepulse'
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]
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else:
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order_list = [
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'hw_write',
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'sw_write',
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'sw_read',
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'singlepulse'
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]
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# Add appropriate else
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order_list_rtl = []
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for i in order_list:
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# Still a loop and not a list comprehension since this might
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# get longer in the future and thus become unreadable
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if len(access_rtl[i]) > 0:
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order_list_rtl = [*order_list_rtl, *access_rtl[i]]
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order_list_rtl.append("else")
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# Remove last pop
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order_list_rtl.pop()
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# Chain access RTL to the rest of the RTL
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self.rtl_header = [*self.rtl_header, *order_list_rtl]
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self.rtl_header.append(
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Field.templ_dict['end_field_ff'].format(
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path = self.path_underscored))
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def __add_ports(self):
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# Port is writable by hardware --> Input port from hardware
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@ -291,6 +347,13 @@ class Field(Component):
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self.dimensions
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))
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# Connect flops to output port
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self.rtl_header.append(
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Field.templ_dict['out_port_assign'].format(
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genvars = self.genvars_str,
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path = self.path_underscored))
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def sanity_checks(self):
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# If hw=rw/sw=[r]w and hw has no we/wel, sw will never be able to write
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if not self.we_or_wel and\
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@ -17,17 +17,57 @@ sw_access_byte: |-
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begin
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{path}_q{genvars}[{msb_field}-:{field_w}] <= sw_wr_bus[{msb_bus}-:{bus_w}];
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end
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hw_access_we_wel: |-
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if ({negl}{path}_hw_wr{genvars})
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hw_access_no_we_wel: |-
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if (1) // we or wel property not set
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// we or wel property not set
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hw_access_field: |-
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begin
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{path}_q{genvars} <= {path}_in{genvars};
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end
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end_field_ff: |-
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end // of {path}'s always_ff
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OnWriteType.woset: |-
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if (byte_enable[{i}]) // woset property
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begin
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{path}_q{genvars}[{msb_field}-:{field_w}] <= {path}_q{genvars}[{msb_field}-:{field_w}] | sw_wr_bus[{msb_bus}-:{bus_w}];
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end
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OnWriteType.woclr: |-
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if (byte_enable[{i}]) // woclr property
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begin
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{path}_q{genvars}[{msb_field}-:{field_w}] <= {path}_q{genvars}[{msb_field}-:{field_w}] & ~sw_wr_bus[{msb_bus}-:{bus_w}];
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end
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OnWriteType.wot: |-
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if (byte_enable[{i}]) // wot property
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begin
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{path}_q{genvars}[{msb_field}-:{field_w}] <= {path}_q{genvars}[{msb_field}-:{field_w}] ^ sw_wr_bus[{msb_bus}-:{bus_w}];
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end
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OnWriteType.wzs: |-
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if (byte_enable[{i}]) // wzs property
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begin
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{path}_q{genvars}[{msb_field}-:{field_w}] <= {path}_q{genvars}[{msb_field}-:{field_w}] & sw_wr_bus[{msb_bus}-:{bus_w}];
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end
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OnWriteType.wzt: |-
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if (byte_enable[{i}]) // wzt property
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begin
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{path}_q{genvars}[{msb_field}-:{field_w}] <= {path}_q{genvars}[{msb_field}-:{field_w}] ~^ sw_wr_bus[{msb_bus}-:{bus_w}];
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end
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OnWriteType.wclr: |-
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{path}_q{genvars} <= {{width{{1'b0}}}};
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OnWriteType.wset: |-
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{path}_q{genvars} <= {{width{{1'b1}}}};
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OnReadType.rclr: |-
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if ({path_wo_field}_sw_rd{genvars}) // rclr property
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begin
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{path}_q{genvars} <= {{width{{1'b0}}}};
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end
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OnReadType.rset: |-
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if ({path_wo_field}_sw_rd{genvars}) // rset property
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begin
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{path}_q{genvars} <= {{width{{1'b1}}}};
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end
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field_comment: |-
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//-----------------FIELD SUMMARY-----------------
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@ -46,4 +86,8 @@ singlepulse: |-
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begin
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{path}{genvars} <= 0;
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end
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out_port_assign: |-
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// Connect register to hardware output port
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assign {path}_r{genvars} <= {path}_q{genvars};
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