srdl2sv

mirror of https://github.com/Silicon1602/srdl2sv.git synced 2024-12-22 06:58:41 +00:00

A SystemRDL 2.0 to (synthesizable) SystemVerilog compiler.

asic fpga hardware-description-language hdl rdl register-description-language registers systemrdl systemrdl-compiler systemverilog verilog

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Dennis 92d61dd7c8 Add onread/onwrite properties to field class This commit also created a seperate private method for access related RTL and for the always_ff header. Furthermore, a bug which caused the singlepulse property to always show up was resolved. Lastly, the summary method was made truely public. So, rather than writing to the RTL list, it now returns a list and the calling method/function can decide what to do with that list.	2021-05-16 12:49:17 +02:00
srdl2sv	Add onread/onwrite properties to field class	2021-05-16 12:49:17 +02:00
.gitignore	Initial commit of SRDL2SV	2021-05-02 00:58:43 +02:00
LIMITATIONS.md	Initial commit of SRDL2SV	2021-05-02 00:58:43 +02:00

Dennis 92d61dd7c8

Add onread/onwrite properties to field class

This commit also created a seperate private method for access related
RTL and for the always_ff header.

Furthermore, a bug which caused the singlepulse property to always show
up was resolved.

Lastly, the summary method was made truely public. So, rather than
writing to the RTL list, it now returns a list and the calling
method/function can decide what to do with that list.

2021-05-16 12:49:17 +02:00

srdl2sv

Add onread/onwrite properties to field class

2021-05-16 12:49:17 +02:00

.gitignore

Initial commit of SRDL2SV

2021-05-02 00:58:43 +02:00

LIMITATIONS.md

Initial commit of SRDL2SV

2021-05-02 00:58:43 +02:00