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Fix issue with read-mux assignment for multidimensional registers

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This commit is contained in:
Dennis Potter 2021-09-12 16:44:37 -07:00
parent 5475bbf62d
commit b89bf3663f
Signed by: Dennis
GPG Key ID: 186A8AD440942BAF
2 changed files with 2 additions and 2 deletions
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2
srdl2sv/components/register.py
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@ -117,7 +117,7 @@ class Register(Component):
if empty_bits > 0:
list_of_fields.append("{}'b0".format(empty_bits))
list_of_fields.append("{}_q".format(field.path_underscored))
list_of_fields.append("{}_q{}".format(field.path_underscored, self.genvars_str))
# Add to appropriate bytes
[bytes_read.add(x) for x in range(field.lsbyte, field.msbyte+1)]

2
srdl2sv/components/templates/register.yaml
View File

@ -83,7 +83,7 @@ sw_data_assignment:
* Assign all fields to signal to Mux *
**************************************/
// Assign all fields. Fields that are not readable are tied to 0.
assign {sw_data_assignment_var_name}{genvars} = {{{list_of_fields}{genvars}}};
assign {sw_data_assignment_var_name}{genvars} = {{{list_of_fields}}};
// Internal registers are ready immediately
assign {sw_rdy_assignment_var_name}{genvars} = {rdy_condition};