Dennis/srdl2sv
1
0
Fork 0
mirror of https://github.com/Silicon1602/srdl2sv.git synced 2024-12-22 15:08:39 +00:00
Code Issues Projects Releases Wiki Activity

Resolve UnboundLocalError bug when SignalNodes are instantiated

Browse Source 
This happened in AddrMap and RegFile because a the width of a new
variable 'new_child' is performed. However, SignalNodes will not create
such a child.
This commit is contained in:
Dennis Potter 2021-10-24 23:17:47 -07:00
parent 27c5931101
commit eb3f1dd57e
Signed by: Dennis
GPG Key ID: 186A8AD440942BAF
2 changed files with 4 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
srdl2sv/components/addrmap.py
View File

@ -54,6 +54,7 @@ class AddrMap(Component):
# Traverse through children # Traverse through children
for child in self.obj.children(): for child in self.obj.children():
print(child)
if isinstance(child, node.AddrmapNode): if isinstance(child, node.AddrmapNode):
# This addressmap opens a completely new scope. For example, # This addressmap opens a completely new scope. For example,
# a field_reset does not propagate through to this scope. # a field_reset does not propagate through to this scope.
@ -76,6 +77,7 @@ class AddrMap(Component):
new_child.sanity_checks() new_child.sanity_checks()
self.mems[child.inst_name] = new_child self.mems[child.inst_name] = new_child
elif isinstance(child, node.RegNode): elif isinstance(child, node.RegNode):
print('here')
if child.inst.is_alias: if child.inst.is_alias:
# If the node we found is an alias, we shall not create a # If the node we found is an alias, we shall not create a
# new register. Rather, we bury up the old register and add # new register. Rather, we bury up the old register and add
@ -94,7 +96,7 @@ class AddrMap(Component):
try: try:
if (regwidth := new_child.get_regwidth()) > self.regwidth: if (regwidth := new_child.get_regwidth()) > self.regwidth:
self.regwidth = regwidth self.regwidth = regwidth
except KeyError: except (KeyError, UnboundLocalError):
# Simply ignore nodes like SignalNodes # Simply ignore nodes like SignalNodes
pass pass

2
srdl2sv/components/regfile.py
View File

@ -85,7 +85,7 @@ class RegFile(Component):
try: try:
if (regwidth := new_child.get_regwidth()) > self.regwidth: if (regwidth := new_child.get_regwidth()) > self.regwidth:
self.regwidth = regwidth self.regwidth = regwidth
except KeyError: except (KeyError, UnboundLocalError):
# Simply ignore nodes like SignalNodes # Simply ignore nodes like SignalNodes
pass pass