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Give all genvars an gv_ prefix to prevent collisions

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This commit is contained in:
Dennis Potter 2021-10-02 00:38:31 -07:00
parent dc37c87944
commit f30dce67c2
Signed by: Dennis
GPG Key ID: 186A8AD440942BAF
4 changed files with 10 additions and 9 deletions
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3
srdl2sv/components/addrmap.py
View File

@ -275,7 +275,8 @@ class AddrMap(Component):
def __append_genvars(self):
genvars = ', '.join([chr(97+i) for i in range(self.get_max_dim_depth())])
genvars = ', '.join([''.join(['gv_', chr(97+i)])
for i in range(self.get_max_dim_depth())])
if genvars:
genvars_instantiation = ''.join([

2
srdl2sv/components/field.py
View File

@ -1189,7 +1189,7 @@ class Field(Component):
self.total_dimensions = len(self.total_array_dimensions)
# Calculate how many genvars shall be added
genvars = ['[{}]'.format(chr(97+i)) for i in range(len(array_dimensions))]
genvars = ['[gv_{}]'.format(chr(97+i)) for i in range(len(array_dimensions))]
self.genvars_str = ''.join(genvars)
# Write enable

6
srdl2sv/components/regfile.py
View File

@ -120,7 +120,7 @@ class RegFile(Component):
self.rtl_footer.append(
self.process_yaml(
RegFile.templ_dict['generate_for_end'],
{'dimension': chr(97+i)}
{'dimension': ''.join(['gv_', chr(97+i)])}
)
)
@ -128,7 +128,7 @@ class RegFile(Component):
self.rtl_header.append(
self.process_yaml(
RegFile.templ_dict['generate_for_start'],
{'iterator': chr(97+i+self.parents_depths),
{'iterator': ''.join(['gv_', chr(97+i+self.parents_depths)]),
'limit': self.array_dimensions[i]}
)
)
@ -174,7 +174,7 @@ class RegFile(Component):
self.dimensions = len(self.array_dimensions)
# Calculate how many genvars shall be added
genvars = ['[{}]'.format(chr(97+i)) for i in range(self.dimensions)]
genvars = ['[gv_{}]'.format(chr(97+i)) for i in range(self.dimensions)]
self.genvars_str = ''.join(genvars)
def create_mux_string(self):

8
srdl2sv/components/register.py
View File

@ -64,7 +64,7 @@ class Register(Component):
for i in range(self.dimensions):
self.rtl_header.append(
Register.templ_dict['generate_for_start'].format(
iterator = chr(97+i+self.parents_depths),
iterator = ''.join(['gv_', chr(97+i+self.parents_depths)]),
limit = self.array_dimensions[i]))
# Add decoders for all registers & aliases
@ -82,7 +82,7 @@ class Register(Component):
for i in range(self.dimensions-1, -1, -1):
self.rtl_footer.append(
Register.templ_dict['generate_for_end'].format(
dimension = chr(97+i)))
dimension = ''.join(['gv_', chr(97+i)])))
if self.dimensions and not self.generate_active:
self.rtl_footer.append("\nendgenerate\n")
@ -524,7 +524,7 @@ class Register(Component):
self.dimensions = len(self.array_dimensions)
# Calculate how many genvars shall be added
genvars = ['[{}]'.format(chr(97+i)) for i in range(self.total_dimensions)]
genvars = ['[gv_{}]'.format(chr(97+i)) for i in range(self.total_dimensions)]
self.genvars_str = ''.join(genvars)
# Determine value to compare address with
@ -532,7 +532,7 @@ class Register(Component):
genvars_sum_vectorized = []
try:
for i, stride in enumerate(self.total_stride):
genvars_sum.append(chr(97+i))
genvars_sum.append(''.join(['gv_', chr(97+i)]))
genvars_sum.append("*")
genvars_sum.append(str(stride))
genvars_sum.append("+")