Add example with aliases
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RTL_TARGETS = $(subst .rdl,.sv,srdl2sv_out/$(shell ls *.rdl))
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.PHONY: clean
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default: verilog_compile
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verilog_compile: $(RTL_TARGETS)
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verilator -cc -sv $(shell ls srdl2sv_out/*.sv)
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srdl2sv_out/%.sv: %.rdl $(shell which srdl2sv)
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srdl2sv $< --out-dir $(shell dirname $@) --stdout-logging INFO -d 31
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clean:
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rm -rf srdl2sv_out
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addrmap aliases {
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///////////////////////////
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// Example SystemRDL LRM //
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///////////////////////////
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reg some_intr_r {
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desc = "This register shows the alias example from Section 10.5.2 of the
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SystemRDL2.0 spec (with some slight adaptations to make it compilable).";
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field {
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level intr;
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hw=w;
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sw=rw;
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woclr;
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} some_event;
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};
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some_intr_r event1;
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// Create an alias for the DV team to use and modify its properties
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// so that DV can force interrupt events and allow more rigorous structural
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// testing of the interrupt.
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alias event1 some_intr_r event1_for_dv;
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event1_for_dv.some_event->woset = true;
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//////////////////////////
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// Example field-subset //
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//////////////////////////
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field field_templ {
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sw = rw;
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hw = rw;
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wel;
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};
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reg four_field_reg {
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desc = "This is a register with 4 fields.";
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field_templ f1 [7:0];
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field_templ f2 [15:8];
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field_templ f3 [23:16];
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field_templ f4 [31:24];
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f3->swmod = true; // swmod does work for aliased registers
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f4->rclr = true; // Show rclr feature
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};
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reg two_field_alias {
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desc = "It is not mandatory that aliases have all fields of the original
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register. A subset of the fields can be made accessible and they
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can have different names.";
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field_templ field_1 [7:0];
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// Removed f2
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// Removed f3
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field_templ field_4 [31:24];
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field_4->woclr = true; // Different option compared to four_field_reg.f1
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};
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four_field_reg four_field_reg; // Actual register
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alias four_field_reg two_field_alias two_field_alias; // Alias with different properties
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};
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/*****************************************************************
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*
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* ███████╗██████╗ ██████╗ ██╗ ██████╗ ███████╗██╗ ██╗
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* ██╔════╝██╔══██╗██╔══██╗██║ ╚════██╗██╔════╝██║ ██║
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* ███████╗██████╔╝██║ ██║██║ █████╔╝███████╗██║ ██║
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* ╚════██║██╔══██╗██║ ██║██║ ██╔═══╝ ╚════██║╚██╗ ██╔╝
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* ███████║██║ ██║██████╔╝███████╗███████╗███████║ ╚████╔╝
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* ╚══════╝╚═╝ ╚═╝╚═════╝ ╚══════╝╚══════╝╚══════╝ ╚═══╝
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*
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* The present RTL was generated by srdl2sv v0.01. The RTL and all
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* templates the RTL is derived from are licensed under the MIT
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* license. The license is shown below.
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*
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* srdl2sv itself is licensed under GPLv3.
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*
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* Maintainer : Dennis Potter <dennis@dennispotter.eu>
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* Report Bugs: https://github.com/Silicon1602/srdl2sv/issues
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*
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* ===GENERATION INFORMATION======================================
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*
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* Generation information:
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* - User: : dpotter
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* - Time : November 06 2021 22:46:49
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* - Path : /home/dpotter/srdl2sv/examples/aliases
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* - RDL file : ['aliases.rdl']
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* - Hostname : ArchXPS
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*
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* RDL include directories:
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* -
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*
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* Commandline arguments to srdl2sv:
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* - Ouput Directory : srdl2sv_out
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* - Stream Log Level : INFO
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* - File Log Level : NONE
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* - Use Real Tabs : False
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* - Tab Width : 4
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* - Enums Enabled : True
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* - Address Errors : True
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* - Unpacked I/Os : True
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* - Register Bus Type: amba3ahblite
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* - Address width : 32
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* - Byte enables : True
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* - Descriptions : {'AddrMap': True, 'RegFile': True, 'Memory': True, 'Register': True, 'Field': True}
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*
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* ===LICENSE OF ALIASES.SV=====================================
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*
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* Copyright 2021 Dennis Potter <dennis@dennispotter.eu>
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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****************************************************************/
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module aliases
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(
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// Resets
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// Inputs
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input clk ,
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input HRESETn ,
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input [31:0] HADDR ,
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input HWRITE ,
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input [2:0] HSIZE ,
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input [3:0] HPROT ,
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input [1:0] HTRANS ,
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input [32-1:0] HWDATA ,
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input HSEL ,
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input [0:0] event1__some_event_in ,
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input four_field_reg__f1_hw_wr,
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input [7:0] four_field_reg__f1_in ,
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input four_field_reg__f2_hw_wr,
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input [7:0] four_field_reg__f2_in ,
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input four_field_reg__f3_hw_wr,
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input [7:0] four_field_reg__f3_in ,
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input four_field_reg__f4_hw_wr,
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input [7:0] four_field_reg__f4_in ,
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// Outputs
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output HREADYOUT ,
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output HRESP ,
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output [32-1:0] HRDATA ,
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output event1_intr ,
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output [7:0] four_field_reg__f1_r ,
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output [7:0] four_field_reg__f2_r ,
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output [7:0] four_field_reg__f3_r ,
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output reg four_field_reg__f3_swmod,
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output [7:0] four_field_reg__f4_r
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);
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// Internal signals
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srdl2sv_widget_if #(.ADDR_W (32), .DATA_W(32)) widget_if;
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/*******************************************************************
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* AMBA 3 AHB Lite Widget
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* ======================
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* Naming conventions
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* - widget_if -> SystemVerilog interface to between widgets
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* and the internal srdl2sv registers.
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* - H* -> Signals as defined in AMBA3 AHB Lite
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* specification
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* - clk -> Clock that drives registers and the bus
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*******************************************************************/
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srdl2sv_amba3ahblite
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#(.FLOP_REGISTER_IF (0),
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.BUS_BITS (32),
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.NO_BYTE_ENABLE (0))
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srdl2sv_amba3ahblite_inst
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(// Bus protocol
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.HRESETn,
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.HCLK (clk),
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.HADDR,
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.HWRITE,
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.HSIZE,
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.HPROT,
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.HTRANS,
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.HWDATA,
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.HSEL,
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.HREADYOUT,
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.HRESP,
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.HRDATA,
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// Interface to internal logic
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.widget_if);
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/*******************************************************************
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/*******************************************************************
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/* REGISTER : event1
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/* DIMENSION : 0
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/* DEPTHS (per dimension): []
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/*******************************************************************
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/*******************************************************************/
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/**REGISTER DESCRIPTION*********************************************
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This register shows the alias example from Section 10.5.2 of the
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SystemRDL2.0 spec (with some slight adaptations to make it compilable).
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/*******************************************************************/
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logic event1_active ;
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logic event1_sw_wr ;
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logic event1_for_dv_active ;
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logic event1_for_dv_sw_wr ;
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logic [31:0] event1_data_mux_in ;
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logic event1_rdy_mux_in ;
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logic event1_err_mux_in ;
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logic [31:0] event1_for_dv_data_mux_in ;
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logic event1_for_dv_rdy_mux_in ;
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logic event1_for_dv_err_mux_in ;
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logic [0:0] event1__some_event_sticky_latch;
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logic [0:0] event1__some_event_q ;
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// Register-activation for 'event1'
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assign event1_active = widget_if.addr == 0;
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assign event1_sw_wr = event1_active && widget_if.w_vld;
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// Register-activation for 'event1_for_dv' (alias)
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assign event1_for_dv_active = widget_if.addr == 4;
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assign event1_for_dv_sw_wr = event1_for_dv_active && widget_if.w_vld;
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//-----------------FIELD SUMMARY-----------------
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// name : some_event (event1[0:0])
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// access : hw = w
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// sw = rw (precedence)
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// reset : - / -
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// flags : ['intr', 'intr type', 'sw', 'woclr']
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// external : False
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// storage type : StorageType.FLOPS
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//-----------------------------------------------
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always_ff @(posedge clk)
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begin
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if (event1_sw_wr)
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begin
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if (widget_if.byte_en[0]) // woclr property
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event1__some_event_q[0:0] <= event1__some_event_q[0:0] & ~widget_if.w_data[0:0];
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end
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else
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if (event1_for_dv_sw_wr)
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begin
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if (widget_if.byte_en[0]) // woset property
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event1__some_event_q[0:0] <= event1__some_event_q[0:0] | widget_if.w_data[0:0];
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end
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else
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begin
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for (int i = 0; i < 1; i++)
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begin
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if (event1__some_event_sticky_latch[i])
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begin
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// Stickybit. Keep value until software clears it
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event1__some_event_q[i] <= 1'b1;
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end
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end
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end
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end // of event1__some_event's always_ff
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// Define signal that causes the interrupt to be set (level-type interrupt)
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assign event1__some_event_sticky_latch = event1__some_event_in;
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/**************************************
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* Register contains interrupts *
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**************************************/
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// Register has at least one interrupt field
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assign event1_intr = |(event1__some_event_q);
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/**********************************************
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* Assign all fields to signal to Mux *
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**********************************************/
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// Assign all fields. Fields that are not readable are tied to 0.
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assign event1_data_mux_in = {{31{1'b0}}, event1__some_event_q};
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// Internal registers are ready immediately
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assign event1_rdy_mux_in = 1'b1;
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// Return an error if *no* read and *no* write was succesful. If some bits
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// cannot be read/written but others are succesful, don't return and error
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// Hence, as long as one action can be succesful, no error will be returned.
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assign event1_err_mux_in = !((widget_if.r_vld && (widget_if.byte_en[0])) || (widget_if.w_vld && (widget_if.byte_en[0])));
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/**********************************************
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* Assign all fields to signal to Mux (alias) *
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**********************************************/
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// Assign all fields. Fields that are not readable are tied to 0.
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assign event1_for_dv_data_mux_in = {{31{1'b0}}, event1__some_event_q};
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// Internal registers are ready immediately
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assign event1_for_dv_rdy_mux_in = 1'b1;
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// Return an error if *no* read and *no* write was succesful. If some bits
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// cannot be read/written but others are succesful, don't return and error
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// Hence, as long as one action can be succesful, no error will be returned.
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assign event1_for_dv_err_mux_in = !((widget_if.r_vld && (widget_if.byte_en[0])) || (widget_if.w_vld && (widget_if.byte_en[0])));
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/*******************************************************************
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/*******************************************************************
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/* REGISTER : four_field_reg
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/* DIMENSION : 0
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/* DEPTHS (per dimension): []
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/*******************************************************************
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/*******************************************************************/
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/**REGISTER DESCRIPTION*********************************************
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This is a register with 4 fields.
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/*******************************************************************/
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logic four_field_reg_active ;
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logic four_field_reg_sw_wr ;
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logic two_field_alias_active ;
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logic two_field_alias_sw_wr ;
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logic four_field_reg__any_alias_sw_wr;
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logic [31:0] four_field_reg_data_mux_in ;
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logic four_field_reg_rdy_mux_in ;
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logic four_field_reg_err_mux_in ;
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logic [31:0] two_field_alias_data_mux_in ;
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logic two_field_alias_rdy_mux_in ;
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logic two_field_alias_err_mux_in ;
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logic [7:0] four_field_reg__f1_q ;
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logic [7:0] four_field_reg__f2_q ;
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logic [7:0] four_field_reg__f3_q ;
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logic [7:0] four_field_reg__f4_q ;
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// Register-activation for 'four_field_reg'
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assign four_field_reg_active = widget_if.addr == 8;
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assign four_field_reg_sw_wr = four_field_reg_active && widget_if.w_vld;
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// Register-activation for 'two_field_alias' (alias)
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assign two_field_alias_active = widget_if.addr == 12;
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assign two_field_alias_sw_wr = two_field_alias_active && widget_if.w_vld;
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// Combined register activation. These will become active on
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// access via any of the alias registers.
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assign four_field_reg__any_alias_sw_wr = four_field_reg_sw_wr || two_field_alias_sw_wr;
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//-----------------FIELD SUMMARY-----------------
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// name : f1 (four_field_reg[7:0])
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// access : hw = rw
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// sw = rw (precedence)
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// reset : - / -
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// flags : ['sw', 'wel']
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// external : False
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// storage type : StorageType.FLOPS
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//-----------------------------------------------
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always_ff @(posedge clk)
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begin
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if (four_field_reg_sw_wr)
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begin
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if (widget_if.byte_en[0])
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four_field_reg__f1_q[7:0] <= widget_if.w_data[7:0];
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end
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else
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if (two_field_alias_sw_wr)
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begin
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if (widget_if.byte_en[0])
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four_field_reg__f1_q[7:0] <= widget_if.w_data[7:0];
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end
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else
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if (!four_field_reg__f1_hw_wr)
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four_field_reg__f1_q <= four_field_reg__f1_in;
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end // of four_field_reg__f1's always_ff
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// Connect register to hardware output port
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assign four_field_reg__f1_r = four_field_reg__f1_q;
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//-----------------FIELD SUMMARY-----------------
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// name : f2 (four_field_reg[15:8])
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// access : hw = rw
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// sw = rw (precedence)
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// reset : - / -
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// flags : ['sw', 'wel']
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// external : False
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// storage type : StorageType.FLOPS
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//-----------------------------------------------
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always_ff @(posedge clk)
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begin
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if (four_field_reg_sw_wr)
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begin
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if (widget_if.byte_en[1])
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four_field_reg__f2_q[7:0] <= widget_if.w_data[15:8];
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end
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else
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if (!four_field_reg__f2_hw_wr)
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four_field_reg__f2_q <= four_field_reg__f2_in;
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end // of four_field_reg__f2's always_ff
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// Connect register to hardware output port
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assign four_field_reg__f2_r = four_field_reg__f2_q;
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//-----------------FIELD SUMMARY-----------------
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// name : f3 (four_field_reg[23:16])
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// access : hw = rw
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// sw = rw (precedence)
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// reset : - / -
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// flags : ['sw', 'wel', 'swmod']
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// external : False
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// storage type : StorageType.FLOPS
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//-----------------------------------------------
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always_ff @(posedge clk)
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begin
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if (four_field_reg_sw_wr)
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begin
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if (widget_if.byte_en[2])
|
||||
four_field_reg__f3_q[7:0] <= widget_if.w_data[23:16];
|
||||
end
|
||||
else
|
||||
if (!four_field_reg__f3_hw_wr)
|
||||
four_field_reg__f3_q <= four_field_reg__f3_in;
|
||||
end // of four_field_reg__f3's always_ff
|
||||
|
||||
// Connect register to hardware output port
|
||||
assign four_field_reg__f3_r = four_field_reg__f3_q;
|
||||
|
||||
// Combinational block to generate swmod-output signals
|
||||
always_comb
|
||||
begin
|
||||
four_field_reg__f3_swmod = 0;
|
||||
four_field_reg__f3_swmod |= four_field_reg__any_alias_sw_wr && |widget_if.byte_en[2:2];
|
||||
end
|
||||
|
||||
|
||||
//-----------------FIELD SUMMARY-----------------
|
||||
// name : f4 (four_field_reg[31:24])
|
||||
// access : hw = rw
|
||||
// sw = rw (precedence)
|
||||
// reset : - / -
|
||||
// flags : ['sw', 'wel', 'rclr']
|
||||
// external : False
|
||||
// storage type : StorageType.FLOPS
|
||||
//-----------------------------------------------
|
||||
|
||||
always_ff @(posedge clk)
|
||||
begin
|
||||
if (four_field_reg_sw_wr)
|
||||
begin
|
||||
if (widget_if.byte_en[3])
|
||||
four_field_reg__f4_q[7:0] <= widget_if.w_data[31:24];
|
||||
end
|
||||
else
|
||||
if (two_field_alias_sw_wr)
|
||||
begin
|
||||
if (widget_if.byte_en[3]) // woclr property
|
||||
four_field_reg__f4_q[7:0] <= four_field_reg__f4_q[7:0] & ~widget_if.w_data[31:24];
|
||||
end
|
||||
else
|
||||
if (!four_field_reg__f4_hw_wr)
|
||||
four_field_reg__f4_q <= four_field_reg__f4_in;
|
||||
end // of four_field_reg__f4's always_ff
|
||||
|
||||
// Connect register to hardware output port
|
||||
assign four_field_reg__f4_r = four_field_reg__f4_q;
|
||||
|
||||
|
||||
|
||||
|
||||
/**********************************************
|
||||
* Assign all fields to signal to Mux *
|
||||
**********************************************/
|
||||
// Assign all fields. Fields that are not readable are tied to 0.
|
||||
assign four_field_reg_data_mux_in = {four_field_reg__f4_q, four_field_reg__f3_q, four_field_reg__f2_q, four_field_reg__f1_q};
|
||||
|
||||
// Internal registers are ready immediately
|
||||
assign four_field_reg_rdy_mux_in = 1'b1;
|
||||
|
||||
// Return an error if *no* read and *no* write was succesful. If some bits
|
||||
// cannot be read/written but others are succesful, don't return and error
|
||||
// Hence, as long as one action can be succesful, no error will be returned.
|
||||
assign four_field_reg_err_mux_in = !((widget_if.r_vld && (|widget_if.byte_en[3:0])) || (widget_if.w_vld && (|widget_if.byte_en[3:0])));
|
||||
|
||||
/**********************************************
|
||||
* Assign all fields to signal to Mux (alias) *
|
||||
**********************************************/
|
||||
// Assign all fields. Fields that are not readable are tied to 0.
|
||||
assign two_field_alias_data_mux_in = {four_field_reg__f4_q, {16{1'b0}}, four_field_reg__f1_q};
|
||||
|
||||
// Internal registers are ready immediately
|
||||
assign two_field_alias_rdy_mux_in = 1'b1;
|
||||
|
||||
// Return an error if *no* read and *no* write was succesful. If some bits
|
||||
// cannot be read/written but others are succesful, don't return and error
|
||||
// Hence, as long as one action can be succesful, no error will be returned.
|
||||
assign two_field_alias_err_mux_in = !((widget_if.r_vld && (widget_if.byte_en[3] || widget_if.byte_en[0])) || (widget_if.w_vld && (widget_if.byte_en[3] || widget_if.byte_en[0])));
|
||||
|
||||
// Read multiplexer
|
||||
always_comb
|
||||
begin
|
||||
unique case (1'b1)
|
||||
event1_active:
|
||||
begin
|
||||
widget_if.r_data = event1_data_mux_in;
|
||||
widget_if.err = event1_err_mux_in;
|
||||
widget_if.rdy = event1_rdy_mux_in;
|
||||
end
|
||||
event1_for_dv_active:
|
||||
begin
|
||||
widget_if.r_data = event1_for_dv_data_mux_in;
|
||||
widget_if.err = event1_for_dv_err_mux_in;
|
||||
widget_if.rdy = event1_for_dv_rdy_mux_in;
|
||||
end
|
||||
four_field_reg_active:
|
||||
begin
|
||||
widget_if.r_data = four_field_reg_data_mux_in;
|
||||
widget_if.err = four_field_reg_err_mux_in;
|
||||
widget_if.rdy = four_field_reg_rdy_mux_in;
|
||||
end
|
||||
two_field_alias_active:
|
||||
begin
|
||||
widget_if.r_data = two_field_alias_data_mux_in;
|
||||
widget_if.err = two_field_alias_err_mux_in;
|
||||
widget_if.rdy = two_field_alias_rdy_mux_in;
|
||||
end
|
||||
default:
|
||||
begin
|
||||
// If the address is not found, return an error
|
||||
widget_if.r_data = 0;
|
||||
widget_if.err = 1;
|
||||
widget_if.rdy = widget_if.r_vld || widget_if.w_vld;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,312 @@
|
|||
/*
|
||||
* Copyright 2021 Dennis Potter <dennis@dennispotter.eu>
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
module srdl2sv_amba3ahblite #(
|
||||
parameter bit FLOP_REGISTER_IF = 0,
|
||||
parameter BUS_BITS = 32,
|
||||
parameter NO_BYTE_ENABLE = 0
|
||||
)
|
||||
(
|
||||
// Bus protocol
|
||||
input HCLK,
|
||||
input HRESETn,
|
||||
input HSEL,
|
||||
input [31:0] HADDR,
|
||||
input HWRITE,
|
||||
input [ 2:0] HSIZE,
|
||||
input [ 3:0] HPROT, // Might be used in the future together with an RDL UDP
|
||||
input [ 1:0] HTRANS,
|
||||
input [BUS_BITS-1:0] HWDATA,
|
||||
|
||||
output logic HREADYOUT,
|
||||
output logic HRESP,
|
||||
output logic [BUS_BITS-1:0] HRDATA,
|
||||
|
||||
// Interface to internal logic
|
||||
srdl2sv_widget_if.widget widget_if
|
||||
);
|
||||
|
||||
localparam BUS_BYTES = BUS_BITS/8;
|
||||
localparam BUS_BYTES_W = $clog2(BUS_BYTES);
|
||||
|
||||
/***********************
|
||||
* Define enums
|
||||
***********************/
|
||||
typedef enum logic [2:0] {
|
||||
SINGLE = 3'b000,
|
||||
INCR = 3'b001,
|
||||
WRAP4 = 3'b010,
|
||||
INCR4 = 3'b011,
|
||||
WRAP8 = 3'b100,
|
||||
INCR8 = 3'b101,
|
||||
WRAP16 = 3'b110,
|
||||
INCR16 = 3'b111
|
||||
} HBURST_t;
|
||||
|
||||
typedef enum logic [1:0] {
|
||||
IDLE = 2'b00,
|
||||
BUSY = 2'b01,
|
||||
NONSEQ = 2'b10,
|
||||
SEQ = 2'b11
|
||||
} HTRANS_t;
|
||||
|
||||
typedef enum logic {
|
||||
OKAY = 1'b0,
|
||||
ERROR = 1'b1
|
||||
} HRESP_t;
|
||||
|
||||
typedef enum logic {
|
||||
READ = 1'b0,
|
||||
WRITE = 1'b1
|
||||
} OP_t;
|
||||
|
||||
typedef enum logic [1:0] {
|
||||
FSM_IDLE = 2'b00,
|
||||
FSM_TRANS = 2'b01,
|
||||
FSM_ERR_0 = 2'b10,
|
||||
FSM_ERR_1 = 2'b11
|
||||
} fsm_t;
|
||||
|
||||
/****************************
|
||||
* Determine current address
|
||||
****************************/
|
||||
logic [31:0] HADDR_q;
|
||||
logic [2:0] HSIZE_q;
|
||||
OP_t operation_q;
|
||||
|
||||
wire addr_err = HADDR % (32'b1 << HSIZE) != 32'b0;
|
||||
|
||||
always_ff @ (posedge HCLK)
|
||||
begin
|
||||
case (HTRANS)
|
||||
IDLE: ;// Do nothing
|
||||
BUSY: ;// Do nothing
|
||||
NONSEQ:
|
||||
begin
|
||||
// When a transfer is extended it has the side-effecxt
|
||||
// of extending the address phase of the next transfer
|
||||
if (HREADYOUT)
|
||||
begin
|
||||
HADDR_q <= HADDR;
|
||||
HSIZE_q <= HSIZE;
|
||||
operation_q <= HWRITE ? WRITE : READ;
|
||||
end
|
||||
end
|
||||
SEQ:
|
||||
begin
|
||||
if (HREADYOUT)
|
||||
begin
|
||||
HADDR_q <= HADDR;
|
||||
HSIZE_q <= HSIZE;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
/****************************
|
||||
* Statemachine
|
||||
****************************/
|
||||
logic [BUS_BITS-1:0] HRDATA_temp;
|
||||
fsm_t fsm_next, fsm_q;
|
||||
|
||||
always_comb
|
||||
begin
|
||||
// Defaults
|
||||
HREADYOUT = 1'b1;
|
||||
HRESP = OKAY;
|
||||
|
||||
// When reading back, the data of the bit that was accessed over the bus
|
||||
// should be at byte 0 of the HRDATA bus and bits that were not accessed
|
||||
// should be masked with 0s.
|
||||
HRDATA_temp = widget_if.r_data >> (8*HADDR_q[BUS_BYTES_W-1:0]);
|
||||
|
||||
for (int i = 0; i < BUS_BYTES; i++)
|
||||
if (i < (1 << HSIZE_q))
|
||||
HRDATA[8*(i+1)-1 -: 8] = HRDATA_temp[8*(i+1)-1 -: 8];
|
||||
else
|
||||
HRDATA[8*(i+1)-1 -: 8] = 8'b0;
|
||||
|
||||
widget_if_w_vld_next = 0;
|
||||
widget_if_r_vld_next = 0;
|
||||
fsm_next = fsm_q;
|
||||
|
||||
case (fsm_q)
|
||||
default: // FSM_IDLE
|
||||
begin
|
||||
if (HSEL && HTRANS > BUSY)
|
||||
begin
|
||||
if (addr_err)
|
||||
// In case the address is illegal, switch to an error state
|
||||
fsm_next = FSM_ERR_0;
|
||||
else if (HTRANS == NONSEQ)
|
||||
// If NONSEQ, go to NONSEQ state
|
||||
fsm_next = FSM_TRANS;
|
||||
else if (HTRANS == SEQ)
|
||||
// If a SEQ is provided, something is wrong
|
||||
fsm_next = FSM_ERR_0;
|
||||
end
|
||||
end
|
||||
FSM_TRANS:
|
||||
begin
|
||||
HREADYOUT = widget_if.rdy;
|
||||
widget_if_w_vld_next = operation_q == WRITE;
|
||||
widget_if_r_vld_next = operation_q == READ;
|
||||
|
||||
if (HTRANS == BUSY)
|
||||
begin
|
||||
// Wait
|
||||
fsm_next = FSM_TRANS;
|
||||
end
|
||||
else if (widget_if.err && widget_if.rdy)
|
||||
begin
|
||||
HREADYOUT = 0;
|
||||
HRESP = ERROR;
|
||||
fsm_next = FSM_ERR_1;
|
||||
end
|
||||
else if (HTRANS == NONSEQ)
|
||||
begin
|
||||
// Another unrelated access is coming
|
||||
fsm_next = FSM_TRANS;
|
||||
end
|
||||
else if (HTRANS == SEQ)
|
||||
begin
|
||||
// Another part of the burst is coming
|
||||
fsm_next = FSM_TRANS;
|
||||
end
|
||||
else if (HTRANS == IDLE)
|
||||
begin
|
||||
// All done, wrapping things up!
|
||||
fsm_next = widget_if.rdy ? FSM_IDLE : FSM_TRANS;
|
||||
end
|
||||
end
|
||||
FSM_ERR_0:
|
||||
begin
|
||||
HREADYOUT = 0;
|
||||
|
||||
if (HTRANS == BUSY)
|
||||
begin
|
||||
// Slaves must always provide a zero wait state OKAY response
|
||||
// to BUSY transfers and the transfer must be ignored by the slave.
|
||||
HRESP = OKAY;
|
||||
fsm_next = FSM_ERR_0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
HRESP = ERROR;
|
||||
fsm_next = FSM_ERR_1;
|
||||
end
|
||||
end
|
||||
FSM_ERR_1:
|
||||
begin
|
||||
if (HTRANS == BUSY)
|
||||
begin
|
||||
// Slaves must always provide a zero wait state OKAY response
|
||||
// to BUSY transfers and the transfer must be ignored by the slave.
|
||||
HREADYOUT = 0;
|
||||
HRESP = OKAY;
|
||||
fsm_next = FSM_ERR_0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
HREADYOUT = 1;
|
||||
HRESP = ERROR;
|
||||
|
||||
fsm_next = FSM_IDLE;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
|
||||
always_ff @ (posedge HCLK or negedge HRESETn)
|
||||
if (!HRESETn)
|
||||
fsm_q <= FSM_IDLE;
|
||||
else
|
||||
fsm_q <= fsm_next;
|
||||
|
||||
/***
|
||||
* Determine the number of active bytes
|
||||
***/
|
||||
logic [BUS_BYTES-1:0] HSIZE_bitfielded;
|
||||
logic [BUS_BYTES-1:0] widget_if_byte_en_next;
|
||||
logic widget_if_w_vld_next;
|
||||
logic widget_if_r_vld_next;
|
||||
|
||||
generate
|
||||
if (NO_BYTE_ENABLE)
|
||||
begin
|
||||
assign widget_if_byte_en_next = {BUS_BYTES{1'b1}};
|
||||
end
|
||||
else
|
||||
begin
|
||||
always_comb
|
||||
begin
|
||||
for (int i = 0; i < BUS_BYTES; i++)
|
||||
HSIZE_bitfielded[i] = i < (1 << HSIZE_q);
|
||||
|
||||
// Shift if not the full bus is accessed
|
||||
widget_if_byte_en_next = HSIZE_bitfielded << (HADDR_q % BUS_BYTES);
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
/***
|
||||
* Drive interface to registers
|
||||
***/
|
||||
generate
|
||||
if (FLOP_REGISTER_IF)
|
||||
begin
|
||||
always_ff @ (posedge HCLK or negedge HRESETn)
|
||||
if (!HRESETn)
|
||||
begin
|
||||
widget_if.w_vld <= 1'b0;
|
||||
widget_if.r_vld <= 1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
widget_if.w_vld <= widget_if_w_vld_next;
|
||||
widget_if.r_vld <= widget_if_r_vld_next;
|
||||
end
|
||||
|
||||
always_ff @ (posedge HCLK)
|
||||
begin
|
||||
widget_if.addr <= {HADDR_q[31:BUS_BYTES_W], {BUS_BYTES_W{1'b0}}};
|
||||
widget_if.w_data <= HWDATA << (8*HADDR_q[BUS_BYTES_W-1:0]);
|
||||
widget_if.byte_en <= widget_if_byte_en_next;
|
||||
end
|
||||
end
|
||||
else
|
||||
begin
|
||||
assign widget_if.w_vld = widget_if_w_vld_next;
|
||||
assign widget_if.r_vld = widget_if_r_vld_next;
|
||||
assign widget_if.addr = {HADDR_q[31:BUS_BYTES_W], {BUS_BYTES_W{1'b0}}};
|
||||
assign widget_if.w_data = HWDATA << (8*HADDR_q[BUS_BYTES_W-1:0]);
|
||||
assign widget_if.byte_en = widget_if_byte_en_next;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
interface srdl2sv_widget_if #(
|
||||
parameter ADDR_W = 32,
|
||||
parameter DATA_W = 32
|
||||
);
|
||||
|
||||
localparam DATA_BYTES = DATA_W >> 3;
|
||||
|
||||
logic [ADDR_W-1:0] addr;
|
||||
logic [DATA_W-1:0] w_data;
|
||||
logic w_vld;
|
||||
logic r_vld;
|
||||
logic [DATA_BYTES-1:0] byte_en;
|
||||
|
||||
logic [DATA_W-1:0] r_data;
|
||||
logic rdy;
|
||||
logic err;
|
||||
|
||||
modport widget (
|
||||
output addr,
|
||||
output w_data,
|
||||
output w_vld,
|
||||
output r_vld,
|
||||
output byte_en,
|
||||
|
||||
input r_data,
|
||||
input rdy,
|
||||
input err
|
||||
);
|
||||
endinterface
|
||||
|
||||
Loading…
Reference in New Issue