5 Commits

Author	SHA1	Message	Date
Dennis	22a822c097	Add initial version of sofware access property tests ... At this point, only the read-side-effect tests are implemented.	2021-10-31 21:56:08 -07:00
Dennis	6719d21423	Fix simple_rw_reg.rdl so that the test passes ... The register was defined as a 64-bit register but the test was written under the assumption it's a 32-bit register. Furthermore, the hardware write-enable flag had to be set since all values would otherwise be overwritten immediately.	2021-10-24 15:43:44 -07:00
Dennis	d3bfdeb3f0	Buswidth is now variable, based on widest register ... Fixes #2.	2021-09-26 21:16:49 -07:00
Dennis	6359883c27	Finish initial version of interrupt suport, closes #1 ... The software is now able to create most interrupt combinations of Section 9.9 of the SystemRDL 2.0 LRM. It supports stickybit/non-stickybit interrupts, it support posedge, negedge, bothedge, and level interrupts, and it is able to generate all surrounding logic. This commit also fixes a reset-bug that caused registers that were reset to 0 to be not reset (because 'if not reset_value' will return True if the 'reset_value' is 0).	2021-09-26 19:40:04 -07:00
Dennis	61cd1fbfe3	Add directory that will contain SystemRDL files for tests	2021-09-13 22:09:04 -07:00